公开(公告)号：DE69934875D1

公开(公告)日：2007-03-08

申请号：DE69934875

申请日：1999-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  DUCOUSSO LAURENT ,  FEL BRUNO

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer system has a plurality of parallel execution units for executing instructions with assigned guard indicators, one execution unit including a master guard value store and another execution unit having a shadow guard value store, together with guard ownership circuitry to indicate whether the shadow guard value store owns the current value of the guard indicator and transfer circuitry operable to transfer a guard value from the master store to another execution unit.

公开(公告)号：FR2856814B1

公开(公告)日：2005-09-30

申请号：FR0307689

申请日：2003-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW

IPC: G06F12/08 ,  G06F12/0864 ,  G06F12/12 ,  G06F12/126

公开(公告)号：GB2362968B

公开(公告)日：2003-12-10

申请号：GB9930589

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  SENAME ISABELLE ,  BERNARD BRUNO ,  WOJCIESZAK LAURENT ,  DEHAMEL ARNAUD

IPC: G06F9/38 ,  G06F11/36 ,  G06F11/07

公开(公告)号：FR2821450A1

公开(公告)日：2002-08-30

申请号：FR0102645

申请日：2001-02-27

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  MERLANDE ANNE ,  FERROUSSAT SEBASTIEN

IPC: G06F9/32 ,  G06F9/38 ,  G06F15/00

Abstract: Method for managing branching instructions at the heart of a processor (CR), which comprises a number of processing units (AU, DU) and a central unit (CU). The central unit assigns instructions to corresponding processing units. A clocking circuit times the processor core (CR), such that each time a branching instruction is received by the central unit it is treated in the same cycle. An Independent claim is made for a processor in which the central unit itself comprising a branching unit, i.e. it is on chip rather than being pipelined as currently. Problems arising with address registers due to this arrangement are solved by checking the validity of the pointer register concerned at the beginning of each cycle and use of a buffer register if necessary.

公开(公告)号：GB2362968A

公开(公告)日：2001-12-05

申请号：GB9930589

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  SENAME ISABELLE ,  BERNARD BRUNO ,  WOJCIESZAK LAURENT ,  DEHAMEL ARNAUD

IPC: G06F9/38 ,  G06F11/36 ,  G06F11/07

Abstract: A system for executing instructions having assigned guard or prediction indicators, the system comprising instruction supply circuitry, at least one pipelined execution unit for receiving instructions from the supply circuitry together with a guard or prediction indicator selected from a set of guard or prediction indicators. The execution unit includes a master guard value store containing master values for the guard indicators and circuitry for resolving the guard or prediction value of the guard or prediction indicator in the instruction pipeline and providing a signal to indicate if the pipeline is committed to executing the instruction. The system includes an emulator which has watch circuitry for watching selected instructions in the execution pipeline and synchronising circuitry for correlating resolution of the guard or prediction indicator of each selected instruction with a program count for that instruction.

公开(公告)号：DE602006005012D1

公开(公告)日：2009-03-19

申请号：DE602006005012

申请日：2006-02-03

Applicant: ST MICROELECTRONICS SA

Inventor： DRUILHE FRANCOIS ,  COFLER ANDREW ,  DUTOIT DENIS ,  HARRAND MICHEL ,  EYZAT GILLES ,  FREUND CHRISTIAN

IPC: G11C11/406

Abstract: The circuit has a refresh controller (48) controlled by a clock signal, and another refresh controller operating during standby periods. A local oscillator (51) receives another clock signal whose frequency is lower than that of the former signal and corresponds to clock frequency of events of global system for mobile communication network. A voltage regulator (59) supplies a memory network during the standby periods. An independent claim is also included for a mobile phone including a mobile phone circuit with a dynamic memory comprising a control circuit.

公开(公告)号：DE69938621D1

公开(公告)日：2008-06-12

申请号：DE69938621

申请日：1999-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  DUCOUSSO LAURENT ,  FEL BRUNO

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer system supplies instructions simultaneously to a plurality of parallel execution pipelines in either superscalar mode or very long instruction word mode with checks for vertical and horizontal dependency between instructions, the horizontal dependency checks between instructions supplied in the same machine cycle being effective in superscalar mode but disabled in very long instruction word mode.

公开(公告)号：DE69934394D1

公开(公告)日：2007-01-25

申请号：DE69934394

申请日：1999-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： WOJCIESZAK LAURENT ,  COFLER ANDREW

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318

Abstract: An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit sequence or the previously supplied bit sequence. If the previously supplied bit sequence is supplied, no power is utilised in that machine cycle.

公开(公告)号：FR2821450B1

公开(公告)日：2004-07-09

申请号：FR0102645

申请日：2001-02-27

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  MERLANDE ANNE ,  FERROUSSAT SEBASTIEN

IPC: G06F9/32 ,  G06F9/38 ,  G06F15/00

Abstract: Method for managing branching instructions at the heart of a processor (CR), which comprises a number of processing units (AU, DU) and a central unit (CU). The central unit assigns instructions to corresponding processing units. A clocking circuit times the processor core (CR), such that each time a branching instruction is received by the central unit it is treated in the same cycle. An Independent claim is made for a processor in which the central unit itself comprising a branching unit, i.e. it is on chip rather than being pipelined as currently. Problems arising with address registers due to this arrangement are solved by checking the validity of the pointer register concerned at the beginning of each cycle and use of a buffer register if necessary.

公开(公告)号：GB2362729B

公开(公告)日：2004-02-11

申请号：GB9930588

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  SENAME ISABELLE ,  BERNARD BRUNO

IPC: G06F9/38

Abstract: A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.