公开(公告)号：DE602005000863D1

公开(公告)日：2007-05-24

申请号：DE602005000863

申请日：2005-07-22

Applicant: ST MICROELECTRONICS SA

Inventor： DEVIN JEAN

IPC: G11C16/34 ,  G11C16/10

公开(公告)号：DE602004005806D1

公开(公告)日：2007-05-24

申请号：DE602004005806

申请日：2004-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： ZINK SEBASTIEN ,  CAVALIERI PAOLA ,  LECONTE BRUNO ,  DEVIN JEAN ,  MAUGAIN FRANCOIS

IPC: G06F12/06 ,  G06F3/06 ,  G11C7/10 ,  G11C8/04 ,  G11C8/12

Abstract: The method involves providing a ready/busy pad contact (RBP) in each sequential access memory. A contact management circuit (RBCT) and a central unit are provided in each memory to force the contact to a predetermined electrical potential. Execution of read or write command for integrated plane memory (MA) in each sequential memory is prevented when the contact presents the predetermined potential. An independent claim is also included for a sequential access memory comprising a serial input/output and an integrated plane memory.

公开(公告)号：FR2847717B1

公开(公告)日：2005-02-11

申请号：FR0214820

申请日：2002-11-26

Applicant: ST MICROELECTRONICS SA

Inventor： DEVIN JEAN

IPC: H02H9/04 ,  H01L29/86 ,  G05F1/46 ,  H03K17/08

公开(公告)号：DE69815590D1

公开(公告)日：2003-07-24

申请号：DE69815590

申请日：1998-03-20

Applicant: ST MICROELECTRONICS SA

Inventor： BRIGATI ALESSANDRO ,  DEVIN JEAN ,  LECONTE BRUNO

IPC: G11C16/02 ,  G06F12/06 ,  G11C7/00 ,  G11C8/12 ,  G11C8/00

Abstract: The IC (1) has two memories (2,3) each controlled by a microprocessor (4,6). Each microcontroller has a circuit (13,14) executing the memory read or write operation. The read or write operations are carried out independent of the selected signal (SS1,SS2). A selection circuit (5) allows one of the memory circuits to be selected.

公开(公告)号：DE69800797T2

公开(公告)日：2001-11-22

申请号：DE69800797

申请日：1998-01-22

Applicant: ST MICROELECTRONICS SA

Inventor： DEVIN JEAN ,  BRIGATI ALESSANDRO ,  LECONTE BRUNO

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/12 ,  G11C16/06

Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.

公开(公告)号：DE69700258T2

公开(公告)日：1999-11-04

申请号：DE69700258

申请日：1997-02-17

Applicant: ST MICROELECTRONICS SA

Inventor： DEVIN JEAN

IPC: G11C11/56

Abstract: The Multi-Level Memory has a matrix (1) of non volatile memory cells (1) memorising two bits of information. The matrix is divided into sectors which are addressable (3,4) and programmable (6,7,8). Read and Write circuits (5) are associated with the matrix. A real time clock (14) updates a command circuit (2) which periodically refreshes (2A) the memory cells.

公开(公告)号：FR2863766A1

公开(公告)日：2005-06-17

申请号：FR0314621

申请日：2003-12-12

Applicant: ST MICROELECTRONICS SA

Inventor： ZINK SEBASTIEN ,  CAVALERI PAOLA ,  LECONTE BRUNO ,  DEVIN JEAN ,  MAUGAIN FRANCOIS

IPC: G11C8/04 ,  G11C8/12 ,  G06F12/02

Abstract: The memory (MEM) has a comparator, an output buffer, and a central unit preventing execution of read or write command if high order address of extended address is different from that of high order address allocated to the memory. The buffer, the unit and the comparator are arranged to allow the memory to effectuate reading of a plane memory (MA) while preventing data read in the memory (MA) from being applied on serial input/output. An independent claim is also included for a method of manufacturing a plane memory addressable with an extended address.

公开(公告)号：FR2795881A1

公开(公告)日：2001-01-05

申请号：FR9908663

申请日：1999-06-30

Applicant: ST MICROELECTRONICS SA

Inventor： DEVIN JEAN ,  CHEHADI MOHAMAD

IPC: G11C16/06 ,  G05F1/00 ,  G06K19/07 ,  G11C16/12 ,  G11C16/30 ,  H02M3/155 ,  H02M3/08 ,  G11C5/14 ,  H04B5/00

Abstract: The invention concerns an integrated circuit comprising a detection circuit (10) and a rectifier circuit (20) associated in series, to supply a rectified voltage (HV1, HV1), and a low voltage regulating circuit (30, 34) which receives the rectified voltage (HV1) and supplies a low voltage (Vcc). The invention is characterised in that the circuit further comprises a voltage producing circuit (100) which receives the rectified voltage (HV1) and produces high voltage (HT) different from the low voltage (Vcc). In one embodiment, the circuit also includes a memory (40) comprising a memory plane (42), the memory plane receiving the low voltage (Vcc) and the high voltage (HT).

公开(公告)号：DE602004005806T2

公开(公告)日：2008-01-10

申请号：DE602004005806

申请日：2004-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： ZINK SEBASTIEN ,  CAVALIERI PAOLA ,  LECONTE BRUNO ,  DEVIN JEAN ,  MAUGAIN FRANCOIS

IPC: G06F12/06 ,  G06F3/06 ,  G11C7/10 ,  G11C8/04 ,  G11C8/12

Abstract: The method involves providing a ready/busy pad contact (RBP) in each sequential access memory. A contact management circuit (RBCT) and a central unit are provided in each memory to force the contact to a predetermined electrical potential. Execution of read or write command for integrated plane memory (MA) in each sequential memory is prevented when the contact presents the predetermined potential. An independent claim is also included for a sequential access memory comprising a serial input/output and an integrated plane memory.

公开(公告)号：FR2874732A1

公开(公告)日：2006-03-03

申请号：FR0409215

申请日：2004-08-31

Applicant: ST MICROELECTRONICS SA

Inventor： DEVIN JEAN

IPC: G11C7/24 ,  G11C16/10 ,  G11C16/34 ,  G11C29/00

Abstract: L'invention concerne un procédé de programmation d'une cellule mémoire présentant une courbe de transconductance (C3) déterminée. La programmation de la cellule mémoire comprend une succession de cycles de programmation comprenant chacun une étape de vérification de l'état de la cellule mémoire. Selon l'invention, l'étape de vérification comprend une première lecture de la cellule mémoire avec une première tension de lecture (Vy1) supérieure à une tension de seuil de référence (VTref), et une seconde lecture de la cellule mémoire avec une seconde tension de lecture (Vy2) inférieure ou égale à la tension de seuil de référence (VTref). La cellule mémoire est considérée comme n'étant pas dans l'état programmé si des courants (I3, I3') de première et de seconde lecture traversant la cellule mémoire sont supérieurs à des seuils déterminés (Iref1, Iref2), et des impulsions de tension de programmation sont appliquées à la cellule mémoire tant que celle-ci n'est pas dans l'état programmé. Application notamment à la programmation de cellules mémoire Flash.