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    Memory device which is electrically programmable in an irreversible manner, comprises matrix of memory cells, each with a transistor and a capacitor with destructible dielectric
    12.
    发明专利
    Memory device which is electrically programmable in an irreversible manner, comprises matrix of memory cells, each with a transistor and a capacitor with destructible dielectric 未知

    公开(公告)号：FR2840444A1

    公开(公告)日：2003-12-05

    申请号：FR0206651

    申请日：2002-05-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  CASPAR DANIEL

    IPC: G11C8/02 ,  G11C17/16 ,  G11C17/14 ,  H01L27/115

    Abstract: The memory device comprises a memory matrix (MM) of memory cells (CLij), each comprising an access transistor and a capacitor whose dielectric is compatible with a technology of type dynamic random-access memory (DRAM). Each row comprises a group of cells (CLi) whose gates of transistors are connected together by a first metallization (WLAi), and whose upper electrodes (ES) of capacitors are connected together by a second metallization (WLPi). Each column comprises a group of cells (CLj) whose sources of transistors are connected together by a third metallization (BLj). The memory control means (MCM) can apply the chosen voltages to the first, second and third metallizations in a manner to program selectively only one cell by breaking down its dielectric without programming other cells and without breaking down the transistors of all cells. A memory cell (CLij) is programmed by applying a gate voltage (Vg) to the first metallization (WLAi), and by applying a voltage difference sufficient to break down the dielectric of capacitor to the second (WLPi) and third (BLj) metallizations; the voltages applied to other metallizations are designed so to block the transistors of other cells of the memory matrix. The transistors of cells are of type n-MOS. The memory control means can apply the chosen voltages to the first, second and third metallizations in a manner to read selectively the logic contents of only one memory cell (CLij) without reading the contents of other memory cells. The memory device (claimed) is implemented in the form of an integrated circuit.

    Semiconductor device for electrically erasable and programmable read-only memory (EEPROM) with only one layer of gate material
    13.
    发明专利
    Semiconductor device for electrically erasable and programmable read-only memory (EEPROM) with only one layer of gate material 未知

    公开(公告)号：FR2838563A1

    公开(公告)日：2003-10-17

    申请号：FR0204690

    申请日：2002-04-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C16/02

    Abstract: The semiconductor memory device comprises a transistor with a floating gate (FG) and a control gate formed by the regions of source (S), drain (D) and channel of the transistor. The memory cell comprises a dielectric zone (ZTN) laid out between a first part (P1) of the layer of gate material and a first active zone (RG1) electrically insulated from a second active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate towards the first active zone at the time of erasing the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) extended between the first part and the ring gate. The first active zone (RG1) and the second active zone (RG2) are electrically insulated one from the other by the p-n junctions polarized in reverse, and on the surface by a region of shallow trench isolation (STI). The two regions of substrate (RG1,RG2) are of the first conductivity type, and the intermediate region (RG3) is of the second conductivity type. The isolation region (RG3) comprises an opening for a contact zone (PSB). The first region of substrate (RG1) comprises a contact zone (PC1) of the first conductivity type. The device also comprises the polarization means possessing the states of programming, reading and erasing the memory cell. The erasing of type Fowler-Nordheim is by applying a voltage to the first active zone much higher than to the regions of source, drain and substrate of the transistor. The programming is by hot carriers at the level of transistor. The programming of type Fowler-Nordheim is by applying to the region of source, drain and substrate the voltages much higher than to the first active zone. The device comprises a memory array incorporating several memory cells, where each memory cell is associated with an access transistor. An integrated circuit comprises the device as claimed.

    14.
    发明专利
    未知

    公开(公告)号：DE60330130D1

    公开(公告)日：2009-12-31

    申请号：DE60330130

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

    15.
    发明专利
    未知

    公开(公告)号：AT449424T

    公开(公告)日：2009-12-15

    申请号：AT03709915

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

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