公开(公告)号：DE69713867T2

公开(公告)日：2003-03-13

申请号：DE69713867

申请日：1997-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： DEYGAS OLIVIER ,  HARRAND MICHEL

IPC: G06T9/00

Abstract: The microprocessor has an operator which is dedicated to calculation of a signature. The operator uses two parameters, with the first a word containing a group of bits from the sequence and the second indicating the length of the group of bits. The operator reacts to the instruction by updating a signature register. The updated signature is the remainder from a polynomial division by a polynomial generator. The dedicated operator has XOR-gates arranged in rows and columns. The number of columns corresponds to the size of the signature register and the number of rows to the maximum length of the group of bits. The appropriate row is selected in response to the second parameter and is transferred to the signature register.

公开(公告)号：DE69525201D1

公开(公告)日：2002-03-14

申请号：DE69525201

申请日：1995-09-04

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  HENRY MICHEL

IPC: G06F13/12 ,  G06F13/16

公开(公告)号：FR2802012A1

公开(公告)日：2001-06-08

申请号：FR9915435

申请日：1999-12-07

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  DOISE DAVID

IPC: G06F12/08 ,  G06F12/0893 ,  G11C7/10 ,  G11C7/22 ,  G06F12/06

Abstract: Two cache memories (A, B) are exclusively used for reading and are connected to a bus (45) and the memory map (2) through ports (52,65). They are also connected to the output (DOUT) by ports (54,58). Two writing cache memories (C,D) receive input (DIN) through ports (64,74) and are connected to the bus (45) by ports (60,70). The writing cache ports are controlled by and gates and place marker registers (80,82)

公开(公告)号：DE69907800T2

公开(公告)日：2004-04-08

申请号：DE69907800

申请日：1999-03-26

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  FERRANT RICHARD

IPC: G11C7/10 ,  G11C7/00

Abstract: The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.

公开(公告)号：FR2801388B1

公开(公告)日：2003-12-12

申请号：FR9914610

申请日：1999-11-19

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL

IPC: G06F12/08 ,  G06F12/0893 ,  G06F12/06 ,  G11C7/22

公开(公告)号：FR2820874B1

公开(公告)日：2003-05-30

申请号：FR0101934

申请日：2001-02-13

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  BULONE JOSEPH

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/406 ,  G11C11/4076 ,  G11C8/00 ,  G06F12/08 ,  G11C11/40

Abstract: A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request and comparing the address of the bank concerned by a current request with the addresses of the N-1 banks previously requested. N is an integral number of cycles necessary for executing a request. If the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N-1 previous requests, then the method further includes steps of suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise the current request is executed.

公开(公告)号：FR2864321B1

公开(公告)日：2007-01-19

申请号：FR0315263

申请日：2003-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL

IPC: G11C11/4091 ,  G01R31/28 ,  G06F11/10 ,  G11C7/10 ,  G11C7/22

Abstract: The memory has a memory plan (2) with an array of memory cells arranged in rows and columns. Two cache memories (5, 6) allow alternative reading of words from a page of the memory and writing of new words in the page. A state machine (105) coupled to the cache memories allow simultaneous read and write access to the plan. An error correction circuit (110) allows reading, modification and writing of the words within the same page. An independent claim is also included for a method of controlling a dynamic random access memory (DRAM).

公开(公告)号：FR2881869A1

公开(公告)日：2006-08-11

申请号：FR0550338

申请日：2005-02-04

Applicant: ST MICROELECTRONICS SA

Inventor： DRUILHE FRANCOIS ,  COFLER ANDREW ,  DUTOIT DENIS ,  HARRAND MICHEL ,  EYZAT GILLES ,  FREUND CHRISTIAN

IPC: G11C11/406 ,  H04M19/08 ,  H04Q7/32

Abstract: L'invention concerne une mémoire dynamique (50) et son application à un circuit de téléphonie mobile avec un circuit de commande comportant un premier contrôleur de rafraîchissement (48) commandé par un premier signal d'horloge (CKIN) et un deuxième contrôleur de rafraîchissement (58) commandé par un deuxième signal d'horloge (LCK) de fréquence inférieure au premier et utilisé pour synchroniser des événements du réseau GSM.

公开(公告)号：FR2864321A1

公开(公告)日：2005-06-24

申请号：FR0315263

申请日：2003-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/22 ,  G01R31/28

Abstract: The memory has a memory plan (2) with an array of memory cells arranged in rows and columns. Two cache memories (5, 6) allow alternative reading of words from a page of the memory and writing of new words in the page. A state machine (105) coupled to the cache memories allow simultaneous read and write access to the plan. An error correction circuit (110) allows reading, modification and writing of the words within the same page. An independent claim is also included for a method of controlling a dynamic random access memory (DRAM).

公开(公告)号：DE69907800D1

公开(公告)日：2003-06-18

申请号：DE69907800

申请日：1999-03-26

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  FERRANT RICHARD

IPC: G11C7/10 ,  G11C7/00

Abstract: The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.