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公开(公告)号：FR2816750A1
公开(公告)日：2002-05-17
申请号：FR0014742
申请日：2000-11-15
Applicant: ST MICROELECTRONICS SA
Inventor： CAVALERI PAOLA , LECONTE BRUNO , ZINK SEBASTIEN , DEVIN JEAN
Abstract: The page-erasable flash memory (MEM1) comprises a flash memory array (FMA), which contains transistors with floating gates connected to the word lines forming pages belonging to sectors (S1,S2...S8), and the control circuits comprising a counter (CMPT) formed by at least one row of transistors, the page address reading circuits including a shift register (SREG), a conversion circuit (CONVC), and a zero-detector (DETZ), and the counter increment circuits including the shift register and a programming register containing latches (LT). The circuits are connected so that the reprogramming of programmed transistors is carried out when the threshold voltage of transistors is below a set verification voltage. The page address reading circuits also comprise the counter word reading circuits including a counter decoder (CDEC), a sense amplifier (SA), the zero-detector, and a column address counter (CAC), the page address high-value bit delivery circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit delivery circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit delivery circuits including the column address counter and a multiplexer (MUX2). The circuits for the counter increment are connected for the programming of at least one counter transistor without erasing other transistors, and the transistor programmed at each increment is the next according to the direction of reading the counter. The page control circuits also comprise a row decoder (XDEC1) and the sense amplifier for reading a word of page by applying the first read voltage (Vread), for reading the same word of page by applying the second read, that is verify, voltage (Vvrfy), for comparing the two readings by a comparator (COMP), and for the reprogramming of transistors if the two readings (W1,W2) are different. The page erasing is by applying a positive erase voltage (Ver+) to the source or the drain electrodes of all transistors of the sector comprising the page. The row decoder (XDEC1) contains adapters for applying a polarization or a negative erase voltage (Vpol,Ver-) to the gates of transistors of the page to be erased, and for applying a positive inhibition or row decoder voltage (Vinhib,Vpcx) to the gates of transistors of one or more pages not to be erased. The adapter circuits receive a page selection signal and deliver the positive voltage (Vpcx) when teh page is not selected and the memory is in the erase mode, or when the page is selected and the memory is not in the erase mode, and the polarization voltage (Vpol), which is below the positive voltage (Vpcx), when the page is selected and the memory is in the erase mode, or when the page is not selected and the memory is not in the erase mode. During the page erasing the polarization voltage (Vpol) is equal to the erase voltage (Ver-) and the positive voltaage (Vpcx) is equal to the inhibition voltage (Vinhib); during the word reading the polarization voltage is equal to the ground potential and the positive voltage is equal to the read voltage. Each adapter circuit contains an output inverter stage and a control stage with an exclusive-OR gate. The positive erase voltage (Ver+) is applied to the source or the drain electrodes of transistors by the intermediary of a material forming the channel of transistors.
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公开(公告)号：DE602004005806D1
公开(公告)日：2007-05-24
申请号：DE602004005806
申请日：2004-12-08
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , CAVALIERI PAOLA , LECONTE BRUNO , DEVIN JEAN , MAUGAIN FRANCOIS
Abstract: The method involves providing a ready/busy pad contact (RBP) in each sequential access memory. A contact management circuit (RBCT) and a central unit are provided in each memory to force the contact to a predetermined electrical potential. Execution of read or write command for integrated plane memory (MA) in each sequential memory is prevented when the contact presents the predetermined potential. An independent claim is also included for a sequential access memory comprising a serial input/output and an integrated plane memory.
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公开(公告)号：DE69815590D1
公开(公告)日：2003-07-24
申请号：DE69815590
申请日：1998-03-20
Applicant: ST MICROELECTRONICS SA
Inventor： BRIGATI ALESSANDRO , DEVIN JEAN , LECONTE BRUNO
Abstract: The IC (1) has two memories (2,3) each controlled by a microprocessor (4,6). Each microcontroller has a circuit (13,14) executing the memory read or write operation. The read or write operations are carried out independent of the selected signal (SS1,SS2). A selection circuit (5) allows one of the memory circuits to be selected.
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公开(公告)号：DE69800797T2
公开(公告)日：2001-11-22
申请号：DE69800797
申请日：1998-01-22
Applicant: ST MICROELECTRONICS SA
Inventor： DEVIN JEAN , BRIGATI ALESSANDRO , LECONTE BRUNO
Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.
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公开(公告)号：DE602004005806T2
公开(公告)日：2008-01-10
申请号：DE602004005806
申请日：2004-12-08
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , CAVALIERI PAOLA , LECONTE BRUNO , DEVIN JEAN , MAUGAIN FRANCOIS
Abstract: The method involves providing a ready/busy pad contact (RBP) in each sequential access memory. A contact management circuit (RBCT) and a central unit are provided in each memory to force the contact to a predetermined electrical potential. Execution of read or write command for integrated plane memory (MA) in each sequential memory is prevented when the contact presents the predetermined potential. An independent claim is also included for a sequential access memory comprising a serial input/output and an integrated plane memory.
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Patent Agency Ranking
公开(公告)号：FR2850201A1
公开(公告)日：2004-07-23
申请号：FR0300615
申请日：2003-01-21
Applicant: ST MICROELECTRONICS SA
Inventor： LECONTE BRUNO , CAVALERI PAOLA , ZINK SEBASTIEN
Abstract: The decoder (WLDEC2) has a group decoder (GPGEN) delivering signals to select word lines (WLi,j) of variable property. A sub-group decoder delivers signal of selection of sub-groups of word lines. The sub-groups have a set of word lines of different groups. Pilots (Di,j) of each word line include a switching transistor to multiplex the selection signals of groups and subgroups for applying a selected signal to a word line.
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公开(公告)号：DE69800797D1
公开(公告)日：2001-06-21
申请号：DE69800797
申请日：1998-01-22
Applicant: ST MICROELECTRONICS SA
Inventor： DEVIN JEAN , BRIGATI ALESSANDRO , LECONTE BRUNO
Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.
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公开(公告)号：DE602004012923T2
公开(公告)日：2009-06-04
申请号：DE602004012923
申请日：2004-05-26
Applicant: ST MICROELECTRONICS SA
Inventor： LECONTE BRUNO , CAVALERI PAOLA , ZINK SEBASTIEN
IPC: G11C16/10
Abstract: The memory has a sequencer (SEQ2) to store sequence of external words in a buffer memory (BMEM2). The sequencer stores internal words present in the page in the buffer memory, erases the page and stores words present in the buffer memory in the erased page. The page is formed by memory cell in a main memory (FMEM2). The buffer memory has the external words and the internal words. An independent claim is also included for a method for storing sequence of external words in a target page of a main memory.
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公开(公告)号：DE60133513D1
公开(公告)日：2008-05-21
申请号：DE60133513
申请日：2001-02-05
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , CAVALERI PAOLA , LECONTE BRUNO
Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.
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公开(公告)号：FR2863764A1
公开(公告)日：2005-06-17
申请号：FR0314622
申请日：2003-12-12
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , CAVALERI PAOLA , LECONTE BRUNO
Abstract: The memory (MEM) has a comparator, an output buffer, and a central unit preventing execution of read or write command if high order address of extended address is different from that of high order address allocated to the memory. The buffer, the unit and the comparator are arranged to allow the memory to effectuate reading of a plane memory (MA) while preventing data read in the memory (MA) from being applied on serial input/output. An independent claim is also included for a method of manufacturing a plane memory addressable with an extended address.
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