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公开(公告)号：FR2841015A1
公开(公告)日：2003-12-19
申请号：FR0207488
申请日：2002-06-18
Applicant: ST MICROELECTRONICS SA
Inventor： TEGLIA YANNICK , LIARDET PIERRE YVAN
Abstract: Method for controlling the execution of a program implementing successive instructions each comprising at least the execution of an operator (OPEj). During the execution of each instruction: a digital signature (SIGN) is determined for each operator taking into account at least a part of an operator digital identification code and at least partially a digital code identifying the position of the operator within the program, without taking into account the values of the instruction operands; and comparison of the calculated signature with an expected value stored in memory. The invention also relates to a corresponding processor for program execution.
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公开(公告)号：FR2829335A1
公开(公告)日：2003-03-07
申请号：FR0111559
申请日：2001-09-06
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN , ROMAIN FABRICE
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公开(公告)号：FR2810438A1
公开(公告)日：2001-12-21
申请号：FR0007762
申请日：2000-06-19
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN , MUSSARD BRUNO
Abstract: The detection circuit has a non-volatile electrically programmable storage circuit (116) and a programming circuit (110) which gradually modifies the programming of the storage circuit with each use. A measuring circuit (120) monitors the storage circuit, and issues an alarm signal when a set number of uses is exceeded.
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公开(公告)号：FR2888370A1
公开(公告)日：2007-01-12
申请号：FR0552047
申请日：2005-07-05
Applicant: ST MICROELECTRONICS SA
Inventor： TEGLIA YANNICK , LIARDET PIERRE YVAN , POMET ALAIN
IPC: G06K19/073 , G06F12/14 , G06F21/75 , G06F21/77
Abstract: L'invention concerne un procédé de protection de l'exécution d'un programme principal (Pg) contre d'éventuels déroutements, comporte les étapes de, lors d'une instruction du programme principal, déclencher un compteur temporel (TIMER) d'un compte donné en fonction d'instructions qui suivent du programme principal, et exécuter une fois que le compteur a atteint son compte au moins une instruction d'un programme secondaire dont dépend le résultat du programme principal.
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公开(公告)号：FR2832824A1
公开(公告)日：2003-05-30
申请号：FR0115361
申请日：2001-11-28
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN
Abstract: A program stored in a non-volatile memory (2) is executed to generate a jump table containing available addresses of an executable RAM (6). A blocking program including sequence of instructions such as RD JUMP, RD INST to proceed with the loop operation of the blocking program, is executed in the executable RAM. An Independent claim is also included for integrated circuit card.
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Patent Agency Ranking16.发明专利
公开(公告)号：FR2829331A1
公开(公告)日：2003-03-07
申请号：FR0111430
申请日：2001-09-04
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN , CHABANNE HERVE
Abstract: A chip card key security system compares (18) a stored (14) intermediate result after X iterations and a random delay with the inverse result from the rest of the N iteration sequence and only confirms the encryption if the results are compatible.
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公开(公告)号：FR2810438B1
公开(公告)日：2002-09-06
申请号：FR0007762
申请日：2000-06-19
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN , MUSSARD BRUNO
Abstract: A circuit to detect the use of an element of an integrated circuit may include a non-volatile electrically programmable storage circuit and a programming circuit. The programming circuit may be used to partially program the storage circuit and gradually modify its programming level as the element is used so that the level represents the number of uses of the element.
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公开(公告)号：FR2790345B1
公开(公告)日：2001-04-27
申请号：FR9902365
申请日：1999-02-25
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN , ROMAIN FABRICE , PLESSIER BERNARD , HENNEBOIS BRIGITTE
Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.
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公开(公告)号：FR2790345A1
公开(公告)日：2000-09-01
申请号：FR9902365
申请日：1999-02-25
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN , ROMAIN FABRICE , PLESSIER BERNARD , HENNEBOIS BRIGITTE
Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.
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公开(公告)号：FR2915007A1
公开(公告)日：2008-10-17
申请号：FR0754405
申请日：2007-04-12
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN , TEGLIA YANNICK
IPC: G06F12/14 , G06F21/54 , G06K19/073
Abstract: L'invention concerne un procédé de contrôle de l'exécution d'au moins un programme (Pg) dans un circuit électronique et un processeur d'exécution d'un programme, dans lequel au moins une zone (AREA) de mémoire volatile (14) du circuit est, préalablement à l'exécution du programme à contrôler, remplie avec des premières instructions (BOP) conduisant à un traitement d'exception ; le programme contient des instructions de remplacement de tout ou partie des premières instructions par des deuxièmes instructions valides ; et ladite zone est appelée (JUMP AREA) pour exécution de tout ou partie des instructions qu'elle contient en fin d'exécution du programme instructions.
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