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    CIRCUIT ELECTRONIQUE EQUIPE POUR EVALUER SA TEMPERATURE, PROCEDE D'EVALUATION DE TEMPERATURE, ET APPLICATIONS
    12.
    发明专利
    CIRCUIT ELECTRONIQUE EQUIPE POUR EVALUER SA TEMPERATURE, PROCEDE D'EVALUATION DE TEMPERATURE, ET APPLICATIONS 未知

    公开(公告)号：FR2874259A1

    公开(公告)日：2006-02-17

    申请号：FR0408853

    申请日：2004-08-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUVAL BENJAMIN ,  POMET ALAIN

    IPC: G01K7/00 ,  G01R31/28

    Abstract: L'invention concerne notamment un circuit électronique (CE) doté d'un oscillateur (OSC_1) délivrant un signal (S1) de fréquence (F1) variable avec la température (Tc) de ce circuit, et recevant ou délivrant un signal (S2) de fréquence (F2) fixe et connue.Ce circuit comprend un module de mesure (MSR) délivrant un signal de mesure (Φ1) représentatif de la fréquence variable (F1) évaluée sur la base du signal (S2) à fréquence fixe pris comme référence ou étalon, et un module de conversion (CVRS) appliquant au signal de mesure (Φ1) une fonction de transfert inverse (u-1, v-1, w-1) de la loi de variation en fonction de la température de la fréquence du premier signal (S1), pour produire un signal de sortie (Θc) représentatif de la température (Tc) du circuit.

    15.
    发明专利
    未知

    公开(公告)号：DE602006005861D1

    公开(公告)日：2009-05-07

    申请号：DE602006005861

    申请日：2006-04-11

    Applicant: ST MICROELECTRONICS SA

    Inventor： ROMAIN FABRICE ,  POMET ALAIN

    IPC: G06F1/00 ,  G06F21/52 ,  G06F21/77 ,  G06F21/79

    Abstract: The method involves calculating a current digital signature of read data with the help of a function taking into account an address (A) of the data in a memory. Coherence between the current signature and a signature previously recorded is verified. The recorded signature is stored in a zone of the memory at the same address as the data. Four groups of temporary storage registers are used for storing the data, the address, the signature extracted from the memory and the current signature.

    16.
    发明专利
    未知

    公开(公告)号：DE602005005002D1

    公开(公告)日：2008-04-10

    申请号：DE602005005002

    申请日：2005-01-05

    Applicant: AXALTO SA ,  ST MICROELECTRONICS SA

    Inventor： LEYDIER ROBERT ,  POMET ALAIN

    IPC: H04L7/033 ,  H04L7/00

    Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.

    17.
    发明专利
    未知

    公开(公告)号：DE60030074D1

    公开(公告)日：2006-09-28

    申请号：DE60030074

    申请日：2000-11-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN ,  PLESSIER BERNARD ,  SOURGEN LAURENT

    IPC: H04L9/08 ,  H04L9/20 ,  H04L9/00 ,  H04L9/10

    Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

    18.
    发明专利
    未知

    公开(公告)号：FR2802733B1

    公开(公告)日：2002-02-08

    申请号：FR9916180

    申请日：1999-12-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN

    IPC: G06K19/073 ,  H03K3/037 ,  H03K3/3562

    Abstract: A master-slave D type flip-flop circuit includes a power consumption masking circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

    19.
    发明专利
    未知

    公开(公告)号：FR2804521A1

    公开(公告)日：2001-08-03

    申请号：FR0001061

    申请日：2000-01-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN ,  MALHERBE ALEXANDRE ,  MARINET FABRICE

    IPC: G06F13/42 ,  G06K19/07 ,  G06F1/04 ,  H04L7/00 ,  H03L7/00

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    20.
    发明专利
    未知

    公开(公告)号：FR2791156B1

    公开(公告)日：2001-05-11

    申请号：FR9903409

    申请日：1999-03-17

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN

    IPC: G06F7/72 ,  G06F7/52 ,  G06F7/50

    Abstract: A coprocessor (200) is proposed, using a single multiplication circuit (228 and 231) coupled to a computation circuit (240) dedicated to the computation of Y0, with Y0=(X*J0)mod 2 , J0 being defined by the equation ((N*J0)+1)mod 2 =0. The computation of Y0 is done bit by bit, during one half-cycle of a clock signal before the use of each bit. A method is also proposed for the computation of a modular operation using the circuit (240) for the computation of Y0.

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