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    12.
    发明专利
    未知

    公开(公告)号：DE69801143T2

    公开(公告)日：2001-11-08

    申请号：DE69801143

    申请日：1998-10-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： NAURA DAVID ,  ZINK SEBASTIEN

    IPC: G11C5/14 ,  G11C16/12 ,  G11C16/30 ,  G11C16/06

    Abstract: The floating grid memory has a high-tension generating circuit for memory programming/erasure with a charge pump for producing a pumped voltage and shaping circuit (2) for supplying a programming or erasing voltage from the pumped voltage. The circuit has control components (5,6,104) to provide control signal (SC) and a commutation circuit (7) to provide a commutated voltage equal to the pumped voltage or a neutral voltage according to the control signal fed to the shaping circuit.

    13.
    发明专利
    未知

    公开(公告)号：FR2803080A1

    公开(公告)日：2001-06-29

    申请号：FR9916445

    申请日：1999-12-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： ZINK SEBASTIEN ,  CAVALERI PAOLA ,  LECONTE BRUNO

    IPC: G11C16/10 ,  G11C16/04 ,  G11C11/4093 ,  G11C7/10

    Abstract: The integrated circuit memory (20) comprises a central memory (10) of FLASH type, which incorporates a set of programming circuit latches (PGRC) provided for recording a word presented at the data input (DIN), without the possibility of simultaneous recording of several words in parallel, also comprises a buffer memory (30) of a sufficient capacity to store a set of words, the means including a Read-Erase Program Central Unit (40), an Address Columns Register (50), and an Address Rows Register (60), for recording in the buffer memory a sequence of words which are to be subsequently recorded in the FLASH memory. The recording means are designed to record a sequence of words in the buffer memory (30) by the application of an address comprising at least N (eg. 8) first bits (a16, ..., a23), equal to N low-value bits of a recording address of the first word, where the applied address is incremented after each word recording, and then to record in the FLASH memory (10) the words already recorded in the buffer memory, by the application of an address comprising M (eg. 16) high-value bits (a0, ..., a15) and N low-value bits, and to the buffer memory an address comprising N low-value bits of address applied to the FLASH memory, where the address applied to the FLASH memory is incremented after each word recording. The N low-value bits correspond to the address of a word in a physical page of the FLASH memory, where the page comprises all words present in a row of words of the FLASH memory. The means for execution of an instruction for recording a set of words comprise an instruction code, a start address in the FLASH memory, and a sequence of words to be recorded (B1, ..., Bm). The memory also comprises a serial/parallel interface circuits (15, 10) for receiving the words to be recorded in the FLASH memory by the intermediary of buffer memory. The memory also comprises the means for the verification of write operation in the FLASH memory, after transfer of words to the FLASH memory and before erasing the buffer memory, by the comparison of words recorded in the FLASH memory and in the buffer memory. The method for recording a sequence of words in the FLASH memory is as in the proposed memory device operation. The received words are in the form of serial data (SDATA), and the serial data are reconstituted in words (PDATA) sent to the input of buffer memory.

    14.
    发明专利
    未知

    公开(公告)号：FR2799045A1

    公开(公告)日：2001-03-30

    申请号：FR9912150

    申请日：1999-09-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： ZINK SEBASTIEN ,  BERTRAND BERTRAND ,  NAURA DAVID

    IPC: G11C16/06 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/02

    Abstract: The integrated circuit memory is of EEPROM type, comprising the data input (D1) and the data output (DO), a planar memory (MM) organized inn words memory (M0-M7), a set of columns registers (LAT) associated with words memory, the first means regarding the write operation for loading the binary data of binary word received at the data input directly to latches (HV0-HV7) of columns register associated with the words memory, and the second means regarding the read operation for a successive reading of binary data stored in the memory cells of words memory and a direct delivery of each binary data in serial form to the data output. The latches for storage and switching (HV0-HV7) comprise each two inverters in antiparallel connection for the storage of binary datum in the form of higher programming voltage or the zero voltage, coupled to the means for conditional switching in the form of two transistors connected in series for carrying the higher programming voltage to the determined bit line, and the loading means in the form of two transistors with the common source connection. The first and second means also comprise the means for an application of selection signals (Bit0-Bit7) to the loading means of latches of each columns register, and the means for loading the data into latches which act via the register selection means in the form of a transistor common to all the latches of the determined columns register. The means for the loading data into latches are common to all columns registers of the memory. The second means comprise a single read line, READLINE, connecting the set of columns registers (LAT) to a read circuit, SENSEAMP. The read circuit comprises only one read amplifier to detect a current flowing in the read line. The memory comprises only one output data line, OUTPUTDATALINE, connecting the output of read circuit to the data output (DO) via a buffer circuit, OUTBUF. The first means comprise only one input data line, INPUTDATALINE, connecting the data input (DI) to the set of columns registers (LAT) via a buffer circuit, INBUF.

    15.
    发明专利
    未知

    公开(公告)号：DE602004006700D1

    公开(公告)日：2007-07-12

    申请号：DE602004006700

    申请日：2004-12-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： ZINK SEBASTIEN ,  CAVALIERI PAOLA ,  LECONTE BRUNO

    IPC: G11C8/04 ,  G06F3/06 ,  G06F12/06 ,  G11C7/10 ,  G11C8/12

    Abstract: The method involves providing a ready/busy pad contact (RBP) in each sequential access memory. A contact management circuit (RBCT) and a central unit are provided in each memory to force the contact to a predetermined electrical potential. Execution of read or write command for integrated plane memory (MA) in each sequential memory is prevented when the contact presents the predetermined potential. An independent claim is also included for a sequential access memory comprising a serial input/output and an integrated plane memory.

    Flash memory erasable by page and method for data storaage, comprising array with counter and sectors, and circuits for reading page address and incrementing counter
    19.
    发明专利
    Flash memory erasable by page and method for data storaage, comprising array with counter and sectors, and circuits for reading page address and incrementing counter 未知

    公开(公告)号：FR2816751A1

    公开(公告)日：2002-05-17

    申请号：FR0014743

    申请日：2000-11-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAVALERI PAOLA ,  LECONTE BRUNO ,  ZINK SEBASTIEN ,  DEVIN JEAN

    IPC: G11C16/06 ,  G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

    Abstract: The page-erasable flash memory (MEM1) comprises a flash memory array (FMA) containing floating-gate transistors whose gates are connected to the word lines, where the transistors connected to the same word line form a page, a row decoder (XDEC1) connected to the word lines, and control circuits which apply a positive erase voltage (Ver+) for a page erasing to the source of the drainn electrodes of all transistors of one of the sectors (S1,S2,...S8) comprisingn the page. The row deecodere contains voltage adapters for applying, during the page erassing, a negative erase voltage (Ver-) to the gates of transistors of the page to be erased, and a positive inhibition voltage (Vinhib) to the gates of transistors of at least one of the other pages. The inhibition voltage is below the positive erase voltage. In the process of the page erasing, a polarization voltage (Vpol) is equal to the negative erase voltage (Ver-) and a row polarization voltage (Vpex) is equa to the inhibition voltage (Vinhib); in the process of word reaading the polarization voltage is equal to the ground potential and the row polarization voltage is equal to a read voltage (Vread). The polarization voltages are delivered by a polarization module (PMP) by the intermediary of a switching element to the voltage adapters receiving the page selection signals and contained in the row deecoder (XDEC1). Each voltage adapter contains an output inverter staage and a control stage with an exclusive-OR gate receiving the selection signal and the erase signal. The circuits for the control of the voltage threshold of transistors and for reprogramming when the voltage threshold is below a set value include a counter (CMPT) formed by at least one row of transistors, the address counter read circuits including a shift register (SREG), a conversion circuit (CONVC) and a zero-detector (DETZ), and the counter increment circuits including the shift register and a register with latches (LT). The page addrses read circuits comprise the counter word-to-word read circuits including a counter decoder (CDEC), a sense amplifier (SA), the zero-detector and a column address counter (CAC), the page address high-value bit circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit circuits including the column address counter and a multiplexer (MUX2). The page control includes the reading of a word of the page by applying the first read voltage (Vread), the reading of the same word of the page by applying the second read, that is verify, voltage (Vvrfy), the comparison of the two readings, and the reprogramming if the two readings are different. The positive erase voltage (Ver+) is applied to the source or the drain electrodes of transistors by the intermediary of a material forming the channel of transistors.

    Flash memory and method for data storage, comprising circuits for control of threshold voltage of memory cells and reprogramming when below set verification value
    20.
    发明专利
    Flash memory and method for data storage, comprising circuits for control of threshold voltage of memory cells and reprogramming when below set verification value 未知

    公开(公告)号：FR2816750A1

    公开(公告)日：2002-05-17

    申请号：FR0014742

    申请日：2000-11-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAVALERI PAOLA ,  LECONTE BRUNO ,  ZINK SEBASTIEN ,  DEVIN JEAN

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

    Abstract: The page-erasable flash memory (MEM1) comprises a flash memory array (FMA), which contains transistors with floating gates connected to the word lines forming pages belonging to sectors (S1,S2...S8), and the control circuits comprising a counter (CMPT) formed by at least one row of transistors, the page address reading circuits including a shift register (SREG), a conversion circuit (CONVC), and a zero-detector (DETZ), and the counter increment circuits including the shift register and a programming register containing latches (LT). The circuits are connected so that the reprogramming of programmed transistors is carried out when the threshold voltage of transistors is below a set verification voltage. The page address reading circuits also comprise the counter word reading circuits including a counter decoder (CDEC), a sense amplifier (SA), the zero-detector, and a column address counter (CAC), the page address high-value bit delivery circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit delivery circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit delivery circuits including the column address counter and a multiplexer (MUX2). The circuits for the counter increment are connected for the programming of at least one counter transistor without erasing other transistors, and the transistor programmed at each increment is the next according to the direction of reading the counter. The page control circuits also comprise a row decoder (XDEC1) and the sense amplifier for reading a word of page by applying the first read voltage (Vread), for reading the same word of page by applying the second read, that is verify, voltage (Vvrfy), for comparing the two readings by a comparator (COMP), and for the reprogramming of transistors if the two readings (W1,W2) are different. The page erasing is by applying a positive erase voltage (Ver+) to the source or the drain electrodes of all transistors of the sector comprising the page. The row decoder (XDEC1) contains adapters for applying a polarization or a negative erase voltage (Vpol,Ver-) to the gates of transistors of the page to be erased, and for applying a positive inhibition or row decoder voltage (Vinhib,Vpcx) to the gates of transistors of one or more pages not to be erased. The adapter circuits receive a page selection signal and deliver the positive voltage (Vpcx) when teh page is not selected and the memory is in the erase mode, or when the page is selected and the memory is not in the erase mode, and the polarization voltage (Vpol), which is below the positive voltage (Vpcx), when the page is selected and the memory is in the erase mode, or when the page is not selected and the memory is not in the erase mode. During the page erasing the polarization voltage (Vpol) is equal to the erase voltage (Ver-) and the positive voltaage (Vpcx) is equal to the inhibition voltage (Vinhib); during the word reading the polarization voltage is equal to the ground potential and the positive voltage is equal to the read voltage. Each adapter circuit contains an output inverter stage and a control stage with an exclusive-OR gate. The positive erase voltage (Ver+) is applied to the source or the drain electrodes of transistors by the intermediary of a material forming the channel of transistors.

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