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    CAPTEUR D'IMAGES A SENSIBILITE AMELIOREE.
    11.
    发明专利
    CAPTEUR D'IMAGES A SENSIBILITE AMELIOREE. 未知

    公开(公告)号：FR2918795A1

    公开(公告)日：2009-01-16

    申请号：FR0756447

    申请日：2007-07-12

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

    Inventor： COUDRAIN PERCEVAL ,  CORONEL PHILIPPE ,  BELREDON XAVIER

    IPC: H01L27/146 ,  H01L31/02 ,  H01L31/18

    Abstract: L'invention concerne un capteur d'images (1) comprenant des cellules photosensibles (B, G, R), chaque cellule photosensible comportant au moins un moyen de stockage de charges (11R, 11G, 11B) formé au moins en partie dans un substrat (9) d'un matériau semiconducteur. Le substrat comprend, pour au moins une première cellule photosensible (B), une portion (10B) d'un premier alliage de silicium et de germanium ayant une première concentration de germanium (XB), éventuellement nulle, et pour au moins une deuxième cellule photosensible (G, R), une portion (10G, 10R) d'un deuxième alliage de silicium et de germanium ayant une deuxième concentration de germanium (XG, XR), non nulle, strictement supérieure à la première concentration de germanium.

    12.
    发明专利
    未知

    公开(公告)号：FR2905519B1

    公开(公告)日：2008-12-19

    申请号：FR0653524

    申请日：2006-08-31

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

    Inventor： CORONEL PHILIPPE ,  MARTY MICHEL

    IPC: H01L21/8236 ,  H01L27/088

    Abstract: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

    FORMING METHOD OF MASK ON INTEGRATED ELECTRONIC CIRCUIT
    13.
    发明专利
    FORMING METHOD OF MASK ON INTEGRATED ELECTRONIC CIRCUIT 审中-公开

    公开(公告)号：JP2006344979A

    公开(公告)日：2006-12-21

    申请号：JP2006160600

    申请日：2006-06-09

    Applicant: ST MICROELECTRONICS CROLLES 2

    Inventor： BUSTOS JESSY ,  THONY PHILIPPE ,  CORONEL PHILIPPE

    IPC: H01L21/027 ,  G03F7/20 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To easily form a circuit member at an upper position of a cavity buried in a substrate, on the substrate of an integrated electronic circuit. SOLUTION: The upper part of the cavity C formed in the substrate 100 of the integrated electronic circuit is closed, and a hollow E is formed. The hollow E is buried by a material 10 selected so that reflection of a lithography radiation F1 may be weakened. If the radiation is irradiated after a resist layer 3 is laminated on the circuit, a portion positioned at the upper part of the hollow E of the resist layer 3 is exposed to a dosage which is lower than a threshold of development of a resist only by primary flux F1. A portion outside the hollow of the resist layer 3 is exposed to the higher dosage than the threshold, by the primary flux F1 and secondary flux F2 reflected from a surface of the substrate 100. When the resist layer 3 is developed, a mask M2 is obtained only at the upper part of the cavity C. COPYRIGHT: (C)2007,JPO&INPIT

    19.
    发明专利
    未知

    公开(公告)号：FR2911721B1

    公开(公告)日：2009-05-01

    申请号：FR0752776

    申请日：2007-01-19

    Applicant: ST MICROELECTRONICS CROLLES 2

    Inventor： CORONEL PHILIPPE ,  FENOUILLET BERANGER CLAIRE

    IPC: H01L21/84 ,  H01L27/12

    Abstract: The device (1) has an upper region (102) including a MOSFET type semiconductor device i.e. P-channel MOS transistor (106), with a metallic gate (108) and arranged on a semiconductor layer (118). A lower region (104) has a MOSFET type semiconductor device i.e. N-channel MOS transistor (134), arranged on a portion (132b) of another semiconductor layer, where the layers are made of strained silicon. The transistor (134) has a gate (128b) formed by a portion of a metallic layer. The latter semiconductor layer is arranged on an insulating layer (146) stacked on another metallic layer (148). An independent claim is also included for a method of manufacturing a silicon-on-insulator MOSFET device.

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