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    12.
    发明专利
    未知

    公开(公告)号：DE69325809D1

    公开(公告)日：1999-09-02

    申请号：DE69325809

    申请日：1993-11-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BALDI LIVIO ,  PIO FEDERICO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: A method for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device provides for charging a capacitor (C;C1-Cn) to a positive high voltage by connecting, through first switching means (TX,TY;TE1-TEn,TF1-TFn), a first plate (A;A1-An) of the capacitor (C;C1-Cn) to a positive high-voltage supply (Vpp) and connecting, through second switching means (TB;TZ;TD1-TDn), a second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn), which is also operatively connected to the control gate of at least one memory cell, to a reference voltage supply (GND), and for successively connecting, through said first switching means (TX,TY;TE1-TEn,TF1-TFn) the first plate (A;A1-An) of the capacitor (C;C1-Cn) to the reference voltage supply (GND) and disconnecting the second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn) from the reference voltage supply (GND) to obtain a negative voltage on said second plate (B;B';B1-Bn) voltage.

    14.
    发明专利
    未知

    公开(公告)号：DE60318419T2

    公开(公告)日：2009-01-02

    申请号：DE60318419

    申请日：2003-07-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRAZZELLI DANIELA ,  BALDI LIVIO ,  SERVALLI GIORGIO

    IPC: H01L21/762

    Abstract: This invention relates to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. The inventive method comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of reducing the vertical height of the substrate and of the field oxide of said first device area.

    15.
    发明专利
    未知

    公开(公告)号：DE69523287D1

    公开(公告)日：2001-11-22

    申请号：DE69523287

    申请日：1995-03-03

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BALDI LIVIO ,  PARUZZI PAOLA

    IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

    Abstract: The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and missing from the second source diffusion. In addition to possessing the known advantages of p-channel EPROM cells such as low consumption and which are still more important in view of the typical applications of FLASH and EEPROM memories they are easier to integrate with MOS transistors of traditional logic circuits because their structure is more similar thereto.

    19.
    发明专利
    未知

    公开(公告)号：DE69722403D1

    公开(公告)日：2003-07-03

    申请号：DE69722403

    申请日：1997-09-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BALDI LIVIO

    IPC: G06K19/077 ,  G07D7/01 ,  G07D7/00

    Abstract: The present invention relates to a currency note (BN) provided with an identification and/or authentication element consisting of an integrated circuit (IC) which can store, securely in electronic form, accessible from outside, such information as: the value, serial number, issuer, and date of issuance.

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