公开(公告)号：DE60318419D1

公开(公告)日：2008-02-14

申请号：DE60318419

申请日：2003-07-11

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAZZELLI DANIELA ,  BALDI LIVIO ,  SERVALLI GIORGIO

IPC: H01L21/762

Abstract: This invention relates to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. The inventive method comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of reducing the vertical height of the substrate and of the field oxide of said first device area.

公开(公告)号：DE60205344D1

公开(公告)日：2005-09-08

申请号：DE60205344

申请日：2002-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  CAPPELLETTI PAOLO ,  GHILARDI TECLA ,  SALI MAURO ,  SERVALLI GIORGIO

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/50

公开(公告)号：ITMI20070270A1

公开(公告)日：2008-08-15

申请号：ITMI20070270

申请日：2007-02-14

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAZZELLI DANIELA ,  COSTANTINI SONIA ,  PAVAN ALESSIA ,  SERVALLI GIORGIO

公开(公告)号：DE602004024560D1

公开(公告)日：2010-01-21

申请号：DE602004024560

申请日：2004-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： SERVALLI GIORGIO ,  BRAZZELLI DANIELA

IPC: H01L27/115 ,  H01L21/28

公开(公告)号：DE60318419T2

公开(公告)日：2009-01-02

申请号：DE60318419

申请日：2003-07-11

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAZZELLI DANIELA ,  BALDI LIVIO ,  SERVALLI GIORGIO

IPC: H01L21/762

Abstract: This invention relates to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. The inventive method comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of reducing the vertical height of the substrate and of the field oxide of said first device area.