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    SUBSTRATE INSULATION DEVICE
    1.
    发明专利
    SUBSTRATE INSULATION DEVICE 失效

    公开(公告)号：JPH065792A

    公开(公告)日：1994-01-14

    申请号：JP2566293

    申请日：1993-02-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONSIGLIO PIETRO ,  ERRATICO PIETRO

    IPC: H01L27/08 ,  H01L27/02

    Abstract: PURPOSE: To maintain a required function, even when a voltage lower than a reference voltage of a substrate is applied to a circuit. CONSTITUTION: This substrate insulating device comprises a power source terminal connected to a terminal 106 of a functional integrated element 100. The element 100 has at least one junction reversely biased, with respect to the substrate 104 specified with the element 100 thereon.

    PROCESS FOR FORMING EMBEDDING CAVITY WITHIN SEMICONDUCTOR MATERIAL WAFER AND EMBEDDING CAVITY
    4.
    发明专利
    PROCESS FOR FORMING EMBEDDING CAVITY WITHIN SEMICONDUCTOR MATERIAL WAFER AND EMBEDDING CAVITY 失效

    公开(公告)号：JP2001291839A

    公开(公告)日：2001-10-19

    申请号：JP2001054817

    申请日：2001-02-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ERRATICO PIETRO ,  SACCHI ENRICO ,  VILLA FLAVIO ,  BARLOCCHI GABRIELE ,  CORONA PIETRO

    IPC: H01L21/822 ,  B81C1/00 ,  G01N37/00 ,  H01L21/306 ,  H01L21/308 ,  H01L21/314 ,  H01L21/316 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To solve the problem that, in forming an embedding cavity within a semiconductor material main body in the prior art, a special mask needed complicates the processes, or increases the cost, or further increas the area where the cavity occupies on silicon. SOLUTION: This process comprises the steps of: forming, on a top part of a semiconductor material wafer, a perforated mask which contains a plurality of openings each having a substantially square shape and a side face having an inclination of 45 deg. with respect to the flat part of the semiconductor material wafer, and has a lattice structure, using the perforated mask to perform anisotropic etching on the semiconductor material wafer in TMAH, thereby forming a cavity having a section of a reverse isosceles trapezoid, and using TEOS to perform a chemical vapor phase growth, thereby forming a TEOS layer which can completely airtightly close the opening of the perforated mask, can define a film coating on the cavity, and can form later a suspended integration structure.

    METHOD FOR FORMING CONTACT PLUG BY BLANKET CVD ATTACHMENT AND ETCH BACK
    5.
    发明专利
    METHOD FOR FORMING CONTACT PLUG BY BLANKET CVD ATTACHMENT AND ETCH BACK 失效

    公开(公告)号：JPH04321224A

    公开(公告)日：1992-11-11

    申请号：JP28066491

    申请日：1991-10-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BALDI LIVIO ,  ERRATICO PIETRO

    IPC: H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768

    Abstract: PURPOSE: To secure flatness of a hole and an insulating layer, without decrease of a filler by overetching a 1st metallic substance, so as to remove a residue of a metallic substance present on an unmasked surface. CONSTITUTION: A tungsten peak of a plug 1, which is coplanar with the surface of an insulating layer 2, is completely masked with a cap 5 of resist. After this masking, etching conditions is corrected more preferably over operation under conditions similar to precedent etching-back conditions for decreasing the anisotropy of etching, thereby over-etching a tungsten residue in an RIE plasma, while increasing the selectivity of an insulating substance (oxide) forming a separate layer 2. For this purpose, a 2nd masked etching-back process of tungsten filling for removing the residue is performed in a mixture of F6 , Cl2 , and Ar and/or under a pressure lower than the 1st etching-back step.

    6.
    发明专利
    未知

    公开(公告)号：IT1261880B

    公开(公告)日：1996-06-03

    申请号：ITMI920338

    申请日：1992-02-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONSIGLIO PIETRO ,  ERRATICO PIETRO

    IPC: H01L27/08 ,  H01L27/02 ,  H01L

    Abstract: A substrate insulation device includes power supply terminals which are connected to a terminal (106) of an active integrated element (100) which has, with respect to a substrate (104) on which it is defined, at least one reverse-biased junction (103).

    8.
    发明专利
    未知

    公开(公告)号：DE69228807T2

    公开(公告)日：1999-08-12

    申请号：DE69228807

    申请日：1992-07-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  ERRATICO PIETRO

    IPC: H04B1/58 ,  H04M1/58 ,  H04M1/76 ,  H04M1/00

    Abstract: A circuit (1) for synthesizing an impedance associated with a telephone subscriber's circuit (2) connected to a two-wire telephone line (3) is a positive feedback configuration comprising: a single precision resistance (R) connected serially to the line (3); at least one low-pass filter; and an amplifier (7) between the filter (8) and the resistance (R). This circuit (1) allows both the termination impedance and the balance impedance to be synthesized through a single external precision component.

    10.
    发明专利
    未知

    公开(公告)号：DE69324621T2

    公开(公告)日：1999-12-09

    申请号：DE69324621

    申请日：1993-02-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONSIGLIO PIETRO ,  ERRATICO PIETRO

    IPC: H01L27/08 ,  H01L27/02

    Abstract: A substrate insulation device includes power supply terminals which are connected to a terminal (106) of an active integrated element (100) which has, with respect to a substrate (104) on which it is defined, at least one reverse-biased junction (103).

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