公开(公告)号：DE69739045D1

公开(公告)日：2008-11-27

申请号：DE69739045

申请日：1997-08-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CASSIO VALERIO ,  CAPRARA PAOLO ,  CEREDA MANLIO SERGIO

IPC: H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

Abstract: The invention relates to a process for manufacturing electronic virtual ground memory devices integrated on a semiconductor and including a matrix (3) of floating gate memory cells, the matrix being formed on a semiconductor substrate (10) with a plurality of continuous bit lines (7) extending across the substrate (10) as discrete parallel stripes. The matrix includes a circuit portion (C') for selection transistors (20), and the memory devices incorporating decode and address circuit portions (A,B) having P-channel and N-channel MOS transistors. The inventive process comprises at least the following steps: forming N-wells (11) in at least one (A) of said substrate portions to accommodate said P-channel transistors, defining the active areas of all the transistors by means of a screening mask (33), and then growing an isolation layer (13) through the apertures of said mask (33). The active area definition mask (33) is not open over the matrix region (C'') of the memory cells.

公开(公告)号：DE69926733D1

公开(公告)日：2005-09-22

申请号：DE69926733

申请日：1999-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  CAPRARA PAOLO

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/522

Abstract: An improved method for autoaligning lines (WL) of a conductive material in circuits integrated on a semiconductor substrate (2), comprising the following steps: forming, on said semiconductor substrate (2), a plurality of regions (3) projecting from the substrate (2) surface and aligned to one another; forming a fill layer (4) in the gaps between said regions (3) ; planarizing said fill layer (4) to expose said regions (3) ; removing a surface portion of said regions (3) to form holes (5) at the locations of said regions (3); forming an insulating layer (6) in said holes (5); selectively removing the dielectric layer (6) to form spacers (7) along the edges of said holes (5) ; depositing at least one conductive layer (8) all over the exposed surface; photolithographing with a mask and etching away the layer (8) to define lines (WL) and collimate them to the underlying regions (3).

公开(公告)号：DE69231484T2

公开(公告)日：2001-02-08

申请号：DE69231484

申请日：1992-11-02

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO ,  LAURIN ENRICO ,  RAVAGLIA ANDREA

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/82

Abstract: A process for producing integrated circuits comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) having a given type of conductivity (P); depositing a polycrystalline silicon layer (14) on the substrate; shaping the polycrystalline silicon layer through a mask (20); and selectively implanting (21) ions of the same conductivity type (P) as the substrate (1) using the shaping mask (20) and through the field insulating regions (10), the implanted ions penetrating inside the substrate (1) having the given type of conductivity (P), for forming channel stopper regions (8') beneath the field insulating regions.

公开(公告)号：DE69231484D1

公开(公告)日：2000-11-02

申请号：DE69231484

申请日：1992-11-02

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO ,  LAURIN ENRICO ,  RAVAGLIA ANDREA

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/82

Abstract: A process for producing integrated circuits comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) having a given type of conductivity (P); depositing a polycrystalline silicon layer (14) on the substrate; shaping the polycrystalline silicon layer through a mask (20); and selectively implanting (21) ions of the same conductivity type (P) as the substrate (1) using the shaping mask (20) and through the field insulating regions (10), the implanted ions penetrating inside the substrate (1) having the given type of conductivity (P), for forming channel stopper regions (8') beneath the field insulating regions.

公开(公告)号：DE69737947D1

公开(公告)日：2007-09-06

申请号：DE69737947

申请日：1997-05-20

Applicant: ST MICROELECTRONICS SRL

Inventor： STUCCHI ELENA ,  DAFFRA STEFANO ,  CEREDA MANLIO SERGIO

IPC: H01L21/00 ,  H01L27/04 ,  H01L21/02 ,  H01L21/329 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/8605

Abstract: The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips (14) for constituting the gate electrodes of the MOS transistors and portions (16) defining openings (17) for the formation of resistors, low-dose ionic implantation (18) through the implantation mask to form pairs of regions (19, 20) at the sides of the gate strips (14) and resistive regions (21) through the openings, the formation of an insulating layer (30) on the entire structure thus produced, and anisotropic etching of the insulating layer (30) so as to uncover the areas of the substrate not covered by the polycrystalline silicon mask but leaving a residue (22) of insulating material along the edges of the gate strips (14). To compensate for the removal of a surface layer from the resistive regions due to the anisotropic etching, a second low-dose implantation is carried out without masking of the substrate, with a dose and an energy such as to produce a predetermined resistivity for the resistive regions (21) without altering the resistivities of the source and drain regions of the MOS transistors.