公开(公告)号：DE69232311D1

公开(公告)日：2002-01-31

申请号：DE69232311

申请日：1992-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CRISENZA GIUSEPPE ,  CLEMENTI CESARE

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L21/28

Abstract: A method comprising the steps of depositing a first (12) and second (17) polysilicon layer, separated by an oxide layer (13); selectively etching the second polysilicon layer (17) to form first gate regions (18); forming first substrate regions (26, 29) in the substrate (2) and laterally in relation to the first gate regions; selectively etching the first polysilicon layer (12) to form second gate regions of a length greater than the first gate regions (18); and forming, in the substrate, laterally in relation to the second gate regions (12) and partially overlapping the first substrate regions (26, 29), second substrate regions (37, 38) of a higher doping level than the first substrate regions (26, 29).

公开(公告)号：DE69705387D1

公开(公告)日：2001-08-02

申请号：DE69705387

申请日：1997-04-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CEROFOLINI GIANFRANCO ,  DE SANTI GIORGIO ,  CRISENZA GIUSEPPE

IPC: C01B33/12 ,  C08F292/00 ,  C08L51/10 ,  H01B3/30 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is composed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

公开(公告)号：DE69325442T2

公开(公告)日：1999-12-16

申请号：DE69325442

申请日：1993-03-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: To reduce the number of depleted cells (21) and the errors caused thereby, the memory array (20) comprises a number of groups of control transistors (23) relative to respective groups (22) of memory cells. The control transistors (23) of each group are NMOS transistors having the drain terminal connected to its own control line (BLP), and each of the control transistors of one group is relative to a row portion of the memory array (20): More specifically, each control transistor (23) presents the control gate connected to the respective word line (WL), and the source region connected to the source region of the cells (21) in the same row and in the same group (22).