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    MOS TECHNIQUE HIGH-SPEED ELECTRIC POWER DEVICE OF INTEGRATEDSTRUCTURE AND ITS PREPARATION
    11.
    发明专利
    MOS TECHNIQUE HIGH-SPEED ELECTRIC POWER DEVICE OF INTEGRATEDSTRUCTURE AND ITS PREPARATION 失效

    公开(公告)号：JPH0846200A

    公开(公告)日：1996-02-16

    申请号：JP17871495

    申请日：1995-07-14

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide an MOS technology power device having integrated circuit in which the series resistance of gate can be decreased without increasing the number of gate metal finger parts. SOLUTION: The MOS technology power device of integrated structure comprises a plurality of functional units of basic component formed in a lightly doped first conductivity type semiconductor layer 1 wherein the functional unit has a second conductivity type channel region 6 coated with a conductive insulation gate layer 8 including a polysilicon layer 5. The conductive insulation gate layer 8 has resistivity significantly lower than that of the polysilicon layer 5 superposed by a highly conductive layer 9. Since a resistance introduced by the polysilicon layer 5 is shunted by a resistance introduced by the highly conductive layer 9, total resistivity of the conductive insulation gate layer 8 is decreased.

    MANUFACTURE OF INTEGRATED EDGE STRUCTURE FOR HIGH VOLTAGE SEMICONDUCTOR DEVICE AND INTEGRATED EDGE STRUCTURE
    12.
    发明专利
    MANUFACTURE OF INTEGRATED EDGE STRUCTURE FOR HIGH VOLTAGE SEMICONDUCTOR DEVICE AND INTEGRATED EDGE STRUCTURE 失效

    公开(公告)号：JP2000183350A

    公开(公告)日：2000-06-30

    申请号：JP34835599

    申请日：1999-12-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRISINA FERRUCCIO

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of an integrated edge structure for a high voltage semiconductor device. SOLUTION: A first conductivity-type (n-type) first semiconductor layer 41 is formed, and a first mask is formed on the upper face. A part of the mask is removed, and at least one opening is formed in the mask. Second conductivity- type impurities are introduced into the first semiconductor layer 41 through an opening, the first mask is completely removed and an N-type second semiconductor layer 42 is formed on the first semiconductor layer. The impurities implanted into the first semiconductor layer are diffused, and a P-type doped region 220 is formed in the first and second semiconductor layers. Final edge structure provided with plural N-type overlap semiconductor layers 41-46, and two inserted columns in plural overlap semiconductor layers formed of the overlap of plural P-type doped regions 220-260 implanted from the opening is formed by repeating six processes once or more. The column near the high- voltage semiconductor device is deeper than the column far from the device.

    MANUFACTURE OF MOS TYPE ELECTRIC POWER DEVICE
    14.
    发明专利
    MANUFACTURE OF MOS TYPE ELECTRIC POWER DEVICE 失效

    公开(公告)号：JPH0817849A

    公开(公告)日：1996-01-19

    申请号：JP15598395

    申请日：1995-06-22

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

    Abstract: PURPOSE: To reduce the manufacturing process of the channel region of a basic function unit and to reduce the ON resistance of a power device by forming the deep body part and the channel part of a body region only by ion implantation without performing any thermal diffusion treatment. CONSTITUTION: After a first dopant is selectively ion-implanted into a heavily doped part 5 in a direction that orthogonally crosses a semiconductor surface with a proper amount of dosage and an energy of ion implantation with an insulation gate layer 8 as a mask, a second dopant is selectively ion-implanted into a region 6 along a direction that is inclined at a prescribed angle in an orthogonally crossed direction, thus forming a body region 2. Then, a large dosage of third dopant is ion-implanted into the greatly doped part 5 to form a source region 7 that is nearly aligned to the edge part of the insulation gate layer 8, thus reducing the manufacturing process of the channel region of a basic function unit since no thermal diffusion treatment is made and reducing the on resistance of a power device.

    POWER ELECTRONIC DEVICE OF MULTI-DRAIN TYPE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND RELATIVE MANUFACTURING PROCESS
    16.
    发明申请
    POWER ELECTRONIC DEVICE OF MULTI-DRAIN TYPE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND RELATIVE MANUFACTURING PROCESS 审中-公开
    集成在半导体基板和相关制造工艺上的多排型电力电子设备

    公开(公告)号：WO2006089725A2

    公开(公告)日：2006-08-31

    申请号：PCT/EP2006001591

    申请日：2006-02-22

    Applicant: ST MICROELECTRONICS SRL ,  SAGGIO MARIO GIUSEPPE ,  FRISINA FERRUCCIO

    Inventor： SAGGIO MARIO GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36

    CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095

    Abstract: Power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising: a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100), a column region (50) of the first type of conductivity realised in said semiconductor layer (20) below the body region (40), wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21, 22, 23, 24), overlapped on each other, wherein the resistivity of each layer is different from that of the other layers and in that said column region (50) comprises a plurality of doped sub-regions (51, 52, 53, 54), each realised in one of said semiconductor layers (21, 22, 23, 24), wherein the amount of charge of each doped sub-regions (51, 52, 53, 54) balances the amount of charge of the semiconductor layer (21, 22, 23, 24) wherein each doped sub-region (51, 52, 53, 54) is realised.

    Abstract translation: 集成在包括多个元件单元的第一导电类型的半导体衬底（100）上的功率电子器件（30），每个元件单元包括：实现在半导体层上的第二导电类型的体区（40） 20），形成在半导体衬底（100）上的第一类型导电体的第一类型的导电体（50），在所述半导体层（20）内实现的第一类型导电体的列区域（50），其中半导体层（ 20）包括彼此重叠的多个半导体层（21,22,23,24），其中每个层的电阻率不同于其它层的电阻率，并且所述列区域（50）包括多个 掺杂子区域（51,52,53,54），其分别在所述半导体层（21,22,23,24）之一中实现，其中每个掺杂子区域（51,52,53,54） 54）平衡半导体层（21,22,23,24）的电荷量 实现了每个掺杂子区域（51,52,53,54）。

    METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES
    17.
    发明申请
    METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES 审中-公开
    用于制造集成在半导体衬底和相应器件中的电子器件的方法

    公开(公告)号：WO2007006504A2

    公开(公告)日：2007-01-18

    申请号：PCT/EP2006006672

    申请日：2006-07-07

    Applicant: ST MICROELECTRONICS SRL ,  FRISINA FERRUCCIO ,  SAGGIO MARIO GIUSEPPE ,  MAGRI ANGELO

    Inventor： FRISINA FERRUCCIO ,  SAGGIO MARIO GIUSEPPE ,  MAGRI ANGELO

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

    CPC classification number: H01L29/1095 ,  H01L21/046 ,  H01L21/047 ,  H01L29/1045 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/6653 ,  H01L29/7802 ,  H01L29/7835

    Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1, 1a; 10, 11) with wide band gap comprising the steps of: forming a screening structure (3a, 20) on said semiconductor substrate (1, 1a; 10, 11) comprising at least a dielectric layer (2, 20) which leaves a plurality of areas of said semiconductor substrate (1, 1a; 10, 11) exposed, carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a first implanted region (4, 40), carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a second implanted region (6, 6c; 60, 61) inside said at least a first implanted region (4, 40), carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4, 40; 6, 60).

    Abstract translation: 在具有宽带隙的半导体衬底（1,1a; 10,11）上制造电子器件的方法包括以下步骤：在所述半导体衬底（1,1a; 10,11）上形成屏蔽结构（3a，20），包括： 至少一个留下所述半导体衬底（1,1a; 10,11）的多个区域的介电层（2,20），所述多个区域暴露在所述半导体衬底（1）中至少进行第一类型的掺杂剂的离子注入 ，1a; 10,11）以形成至少第一注入区域（40,40），在所述半导体衬底（1,1a; 10,11）中至少执行第二类型的掺杂剂的离子注入以形成 在所述至少第一注入区域（4,40）内部的至少一个第二注入区域（6,6c; 60,61）中，执行所述第一类型和第二类型的掺杂剂的激活热过程，其具有适合于完成 所述至少第一和第二植入区域（4,40; 6,60）的形成。

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