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    15.
    发明专利
    未知

    公开(公告)号：DE602004021599D1

    公开(公告)日：2009-07-30

    申请号：DE602004021599

    申请日：2004-09-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARTINES IGNAZIO ,  LA PLACA MICHELE

    IPC: G11C16/28

    Abstract: Described herein is a reading circuit (5) for a nonvolatile memory device (1), wherein the currents flowing through an array memory cell (12) to be read, and a reference memory cell (15) with known contents, are converted into an array voltage (V M ) and, respectively, into a reference voltage (V R ), which are compared to determine the contents of the array memory cell (12). The method envisages reducing the electrical stress to which the reference memory cell (15) is subjected during reading, by generating and holding a sample (V 2 ) of the reference voltage (V R ), then deselecting the reference memory cell (15), and then continuing reading using the sample (V 2 ) of the reference voltage (V R ).

    17.
    发明专利
    未知

    公开(公告)号：DE602004004597D1

    公开(公告)日：2007-03-22

    申请号：DE602004004597

    申请日：2004-10-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PISASALE MICHELANGELO ,  GAIBOTTI MAURIZIO ,  LA PLACA MICHELE

    IPC: G11C5/14 ,  G11C16/30

    Abstract: A voltage-down converter ( 125 ) for providing an output voltage (Vo) lower than a power supply voltage (Vdd) of the converter is proposed. The converter includes voltage regulation means ( 205 ) for obtaining an intermediate voltage (Vr) corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element ( Tr ) with a control signal (Vg) resulting from a comparison between the intermediate voltage (Vr) and a reference voltage (Vbg), and an output stage ( 220,225 1 - 225 N ) for obtaining the output voltage from the power supply voltage by controlling a further variable-conductivity element ( Tsb,T 1 - T N ) with the control signal, wherein the further variable-conductivity element has a modular structure with at least one set ( MM,ML,MH ) of multiple basic modules ( 225 1 - 225 N ), the converter further including means ( 230,SW 1 - SW N ) for enabling and/or disabling the modules of each set in succession according to a comparison between the output voltage and the intermediate voltage.

    18.
    发明专利
    未知

    公开(公告)号：IT1307687B1

    公开(公告)日：2001-11-14

    申请号：ITTO990291

    申请日：1999-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONDEMI CARMELO ,  LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: G11C7/12 ,  G11C16/28 ,  G11C16/32

    Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.

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