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    13.
    发明专利
    未知

    公开(公告)号：DE60301851D1

    公开(公告)日：2005-11-17

    申请号：DE60301851

    申请日：2003-02-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARTINES IGNAZIO ,  TORRISI DAVIDE

    IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

    Abstract: The present invention relates to a gate voltage regulation system for the programming and/or soft programming phase of non volatile memory cells, for example of the Flash type, with low circuit area occupation, wherein memory cells (5) are organised in cell matrices with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content; the cells having gate terminals (G) biased in the programming phase with a predetermined voltage value by means of charge pump voltage regulators. Advantageously, a first (ST1) and a second (ST2) regulation stages are provided, being structurally independent, responsible for the programming and soft programming phase respectively; the first stage (ST1) generating a supply voltage for said second stage (ST2).

    14.
    发明专利
    未知

    公开(公告)号：IT1307686B1

    公开(公告)日：2001-11-14

    申请号：ITTO990290

    申请日：1999-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONDEMI CARMELO ,  LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: G11C16/28

    Abstract: A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.

    16.
    发明专利
    未知

    公开(公告)号：DE60325453D1

    公开(公告)日：2009-02-05

    申请号：DE60325453

    申请日：2003-02-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARTINES IGNAZIO ,  SCARDACI MASSIMO

    IPC: G11C11/56 ,  G11C16/12

    Abstract: The invention relates to a voltage regulation system for multiword programming in non volatile memories, for example of the Flash type, with low circuit area occupation, wherein memories comprise at least a memory cell matrix (5) organised in cell rows and columns and with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. Memory cells have drain terminals (D) connected to matrix columns and biased in the programming step with a predetermined voltage value by means of program load circuits (2) associated to each matrix column; advantageously, the invention provides, in parallel with each program load circuit (2), a conduction-to-ground path (9) enabled by a controlled active element (10).

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