公开(公告)号：ITMI20060350A1

公开(公告)日：2007-09-01

申请号：ITMI20060350

申请日：2006-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： GIAMBARTINO ANTONIO ,  LA PLACA MICHELE ,  MARTINES IGNAZIO

公开(公告)号：DE60214868D1

公开(公告)日：2006-11-02

申请号：DE60214868

申请日：2002-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI PAOLINO ,  POLI SALVATORE ,  GIAMBARTINO ANTONIO ,  LA MALFA ANTONINO ,  POLIZZI SALVATORE

IPC: G11C16/10 ,  G11C16/12

Abstract: The invention relates to a circuit architecture and a method for performing a page programming in non volatile memory electronic devices equipped with a memory cell matrix (3) and an SPI serial communication interface (2), as well as circuit portions associated to the cell matrix (3) and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank (5) is provided to store and draw data during the page programming in the pseudo-serial mode through said interface (2). Data latching is performed one bit at a time and the following data retrieval occurs instead with at least two bytes at a time.