公开(公告)号：DE69322384T2

公开(公告)日：1999-05-12

申请号：DE69322384

申请日：1993-09-10

Applicant: ST MICROELECTRONICS SRL

Inventor： GHEZZI PAOLO ,  MAURELLI ALFONSO

IPC: H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866

Abstract: A process for the manufacture of a zener-diode as an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well (2) on a single-crystal silicon substrate (1); a step of formation of an active area (4) on the surface of said N type well (2); a step of growth of a thin gate oxide layer (5) over said active area (4); a step of implantation of a first heavy dose of N type dopant into said N type well (2) to obtain an N type region (6; 18; 19); a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region (6; 18) to obtain an N+ contact region (7; 20) to both the N type well (2) and said N type region (6; 18; 19); a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region (6; 19) to form a P+ region (8; 21). The N+ region (7; 20) is of annular shape. The zener-diode can also be gated. All manufacturing steps for the zener-diode correspond to manufacturing steps of the flash EEPROM memory device.

公开(公告)号：DE69732637T2

公开(公告)日：2005-12-29

申请号：DE69732637

申请日：1997-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO ,  MAURELLI ALFONSO ,  OLIVO MARCO

IPC: G06F11/10 ,  G11C29/00 ,  G11C16/06 ,  G11C29/06 ,  G11C29/52

Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

公开(公告)号：DE69624107T2

公开(公告)日：2003-06-05

申请号：DE69624107

申请日：1996-07-18

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A flash EEPROM memory cell comprises source and drain regions (71,72,81,82;73,83) defining a channel region therebetween, a floating gate (10) and a control gate (9). The source and drain regions are first and second doped semiconductor regions (71,72,81,82;73,83) of a first conductivity type formed in a first active area region (33) of a semiconductor material layer (1) of a second conductivity type; the control gate comprises a third doped semiconductor region (9) of the first conductivity type formed in a second active area region (34) of the semiconductor material layer (1); and the floating gate comprises a polysilicon strip (10) insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region (9).

公开(公告)号：DE69624107D1

公开(公告)日：2002-11-07

申请号：DE69624107

申请日：1996-07-18

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A flash EEPROM memory cell comprises source and drain regions (71,72,81,82;73,83) defining a channel region therebetween, a floating gate (10) and a control gate (9). The source and drain regions are first and second doped semiconductor regions (71,72,81,82;73,83) of a first conductivity type formed in a first active area region (33) of a semiconductor material layer (1) of a second conductivity type; the control gate comprises a third doped semiconductor region (9) of the first conductivity type formed in a second active area region (34) of the semiconductor material layer (1); and the floating gate comprises a polysilicon strip (10) insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region (9).

公开(公告)号：DE69032937D1

公开(公告)日：1999-03-18

申请号：DE69032937

申请日：1990-07-24

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82 ,  G11C16/04

Abstract: The process provides for the simultaneous N+ type implantation of areas (7, 8, 9) of a semiconductor substrate of type P for the formation of a control gate (9) and of highly doped regions of source (7) and drain (8), defining a channel region (4). After oxide growth (11, 12) there is executed the deposition and the definition of a polysilicon layer (10), one region of which constitutes a floating gate above the control gate (9) and the channel region (4) and partially superimposed over the regions of source (7) and drain (8).

公开(公告)号：ITMI20071140A1

公开(公告)日：2008-12-05

申请号：ITMI20071140

申请日：2007-06-04

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO

公开(公告)号：DE69732637D1

公开(公告)日：2005-04-07

申请号：DE69732637

申请日：1997-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO ,  MAURELLI ALFONSO ,  OLIVO MARCO

IPC: G06F11/10 ,  G11C29/00 ,  G11C16/06 ,  G11C29/06 ,  G11C29/52

Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

公开(公告)号：DE69322384D1

公开(公告)日：1999-01-14

申请号：DE69322384

申请日：1993-09-10

Applicant: ST MICROELECTRONICS SRL

Inventor： GHEZZI PAOLO ,  MAURELLI ALFONSO

IPC: H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866

Abstract: A process for the manufacture of a zener-diode as an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well (2) on a single-crystal silicon substrate (1); a step of formation of an active area (4) on the surface of said N type well (2); a step of growth of a thin gate oxide layer (5) over said active area (4); a step of implantation of a first heavy dose of N type dopant into said N type well (2) to obtain an N type region (6; 18; 19); a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region (6; 18) to obtain an N+ contact region (7; 20) to both the N type well (2) and said N type region (6; 18; 19); a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region (6; 19) to form a P+ region (8; 21). The N+ region (7; 20) is of annular shape. The zener-diode can also be gated. All manufacturing steps for the zener-diode correspond to manufacturing steps of the flash EEPROM memory device.