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    FLASH INTERCHANGEABILITY EEPROM
    1.
    发明专利
    FLASH INTERCHANGEABILITY EEPROM 失效

    公开(公告)号：JP2001057089A

    公开(公告)日：2001-02-27

    申请号：JP2000186781

    申请日：2000-06-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO

    IPC: G11C16/02 ,  G11C11/00 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To enable page erasion having completely interchange ability, that is, adaptability for a standard process by applying negative voltage in which single supply voltage is boosted secondarily to a single word line selected by a row decoder during a erasing phase period, and applying positive voltage- boosted first to a common source of all cells of a block and a separated region of a substrate. SOLUTION: A erasion/write-in control logic circuit 620 drives an adjustor 610 comprising an electric charge pump circuit generating normally negative and positive voltage and a voltage adjustor relating to the circuit and generating the required voltage. Negative boosted voltage generated by the adjustor 610 is supplied to program switches 605A, 605B, row decoders 601A, 601B, source decoders 602A, 602B, and a separated region of a substrate. Algorithm for erasion of a byte erasing block 600B is different from that of a sector erasable block 600A, but each page erasion can be performed by applying pulse sequence of voltage for erasion increased by stages.

    METHOD OF WRITING HOT ELECTRON CONTROLLED FOR NONVOLATILE MEMORY CELLS
    3.
    发明专利
    METHOD OF WRITING HOT ELECTRON CONTROLLED FOR NONVOLATILE MEMORY CELLS 失效

    公开(公告)号：JPH11191296A

    公开(公告)日：1999-07-13

    申请号：JP28774398

    申请日：1998-10-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO ,  RICCO BRUNO ,  ESSENI DAVID

    IPC: G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/12

    Abstract: PROBLEM TO BE SOLVED: To eliminate the need for an additional current limiting circuit by successively controlling programming parameters by writing into cells in an equilibrium between an injection current and a displacement current and forming a best programming of the cells. SOLUTION: To optimize writing into cells, it is made in an equilibirium in which cells have a constant floating gate voltage and current. Especially, to both writing of programming and that of a software after erasure, substrate area of the cells is biased to a negative voltage against a source area, and further, a control gate area of the cells applied with a ramp voltage. The gradient of this ramp voltage is selected so that an equilibirium can be achieved between an injection current made to flow into the floating gate area and a displacement current related to an equivalent capacity existing between the floating gate and the control gate area.

    5.
    发明专利
    未知

    公开(公告)号：DE69732637T2

    公开(公告)日：2005-12-29

    申请号：DE69732637

    申请日：1997-12-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO ,  MAURELLI ALFONSO ,  OLIVO MARCO

    IPC: G06F11/10 ,  G11C29/00 ,  G11C16/06 ,  G11C29/06 ,  G11C29/52

    Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

    7.
    发明专利
    未知

    公开(公告)号：DE69429264D1

    公开(公告)日：2002-01-10

    申请号：DE69429264

    申请日：1994-09-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO ,  CASAGRANDE GIULIO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00 ,  G11C16/06

    Abstract: A byte erasable memory with an EEPROM type functionality that can be integrated in a fully compatible way with a standard FLAS-EPROM process is composed by a matrix of FLASH-EPROM cells organized in an n number of bytes each of an m number of bits addressable through a plurality of wordlines and bitlines. The EEPROM-type memory has an auxiliary selection structure composed of an n number of byte select transistors, a plurality of individually selectable source biasing lines and a plurality of select lines in the same number of the wordlines and selectable in a biunivocal way with the wordlines. The cells of a byte have a common source that is accessed and individually selectable through the respective select transistors. EEPROM functionality is obtained without any modification of the standard FLASH-EPROM fabrication process by splitting the voltage applied between a control gate and the respective common source region of the cells that compose a certain selected byte about a common ground potential, during a byte erasing phase thus reducing the electrical stress induced on deselected cells.

    8.
    发明专利
    未知

    公开(公告)号：DE69923548D1

    公开(公告)日：2005-03-10

    申请号：DE69923548

    申请日：1999-06-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO

    IPC: G11C16/02 ,  G11C11/00 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: A flash compatible EEPROM device has a first flash matrix and a second matrix with EEPROM functionalities of substantially similar layout, both are divided into blocks of cells formed in substrate regions isolated from one another. In said second matrix, the information is organized in pages each one contained in a row of memory cells of one of said block of subdivision of the matrix. A hierarchic structure including a row decoder addresses the wordline of all the cells of a selected row of the block, co-operating with a column decoder in selecting single cells of the rows. A boosted voltage of polarity opposite to the single supply voltage of the device is applied during an erasing phase to a single wordline selected by means of said row decoder, to page-erase said information by applying a boosted voltage to the common source of all the cells of the block and to the isolated region of the substrate containing all the cells of the block. A logical circuit confirms the programmed state of each cell containing a logic zero information of the not erased rows of the block after one or more rows or pages have been erased, applying said first boosted voltage to a wordline at a time and said supply voltage to one or more bitlines at a time for confirming a preexistent programmed state, while keeping to ground voltage the common source of all the cells of the block and the confined isolated region of the substrate.

    10.
    发明专利
    未知

    公开(公告)号：DE69630107D1

    公开(公告)日：2003-10-30

    申请号：DE69630107

    申请日：1996-04-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO

    IPC: G11C17/00 ,  G11C11/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

    Abstract: Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.

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