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公开(公告)号：JP2619615B2
公开(公告)日：1997-06-11
申请号：JP11895
申请日：1995-01-04
Applicant: ST MICROELECTRONICS SRL
Inventor： OLIVO MARCO , PADOAN SILVIA
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公开(公告)号：JPH0896590A
公开(公告)日：1996-04-12
申请号：JP22351795
申请日：1995-08-31
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , PADOAN SILVIA , PASCUCCI LUIGI
Abstract: PROBLEM TO BE SOLVED: To lengthen a lifetime without applying useless stress to a beforehand programmed bit by re-programming only the cell of a bit incapable of being compared with data to be stored. SOLUTION: When the reference signal COMPRECH of a second input terminal 4 is at 'H', the No.i bit signal SOUTi of a 16 bit word read from the cell of a fresh memory is received by a first input terminal 3 through a sense amplifier SA in a comparator 2. When the second control signal DWE of a fourth input terminal 6 is at 'H', an input terminal 9 receives a bit value DBUFi corresponding to No.i cell from a latch holding data to be written to the memory. When the result of the comparison of the signals SOUTi and DBUFi is not correct, the signal DINCOMPi of a second output terminal 13 is at 'H', and a bit to be re-programmed is indicated. Accordingly, only the specified cell of a non-volatile memory is re-programmed.
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13.发明专利
公开(公告)号：JPH0856149A
公开(公告)日：1996-02-27
申请号：JP5377895
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , PASCUCCI LUIGI
IPC: G11C17/00 , G11C16/06 , H01L27/10 , H03K19/177
Abstract: PURPOSE: To reduce an error in reading and to suppress power consumption by reading a programmable logic array for a memory only in a period necessitating reading. CONSTITUTION: PLA1 providing the state machine of a nonvolatile memory is provided with dynamic NAND-NOT-NOR constitution, a timing signal for correctly reading PLA is generated by a clock generator and this generator generates the monostable sequence of reading enabling signals CPPA, CPO and CPM on receiving a predetermined switching edge of an external clock signal CP. This clock generator enables evaluating the AND face 3 and the OR face 4 of PLA and continually enables storage of a result by parts 33, 38 and 48 reproducing the propagation delays of the signals at parts 3 to 5 PLA corresponds to. Reading is finished as soon as the storage step is completed to limit reading only in a necessary period.
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公开(公告)号：JPH07254294A
公开(公告)日：1995-10-03
申请号：JP29488194
申请日：1994-11-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , PADOAN SILVIA
Abstract: PURPOSE: To provide an integrated circuit for programming memory cell in a non-volatile memory register while simplifying configuration and reducing the area to be occupied. CONSTITUTION: Concerning the integrated circuit for programming memory cell in the non-volatile memory register, a memory cell has a control electrode and a supply electrode, and one programmable non-volatile memory cell TF suitable for storing the information of one bit at least and a load circuit LC for reading the information stored in this memory cell are provided. The integrated circuit is provided with a switching means TS serially connected between the supply electrode of the memory cell TF and each data line A for conveying data to be programmed into the memory cell. When programming the memory cell in the non-volatile memory register, this switching means is controlled by a signal 7 for electrically connecting the memory cell TF to the data line A. The data line A is defined as the address signal line of an address signal bus to be used for the decoder circuit of memory matrix as well.
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公开(公告)号：JPH07253830A
公开(公告)日：1995-10-03
申请号：JP11895
申请日：1995-01-04
Applicant: ST MICROELECTRONICS SRL
Inventor： OLIVO MARCO , PADOAN SILVIA
Abstract: PURPOSE: To execute control by means of a reset signal even when a power supply voltage is raised to a steady state value from zero. CONSTITUTION: An electrically programmable nonvolatile storage device 1 is constituted of a memory matrix 2 to which a power supply voltage Vcc and a programming voltage Vpp are supplied, a control logic circuit 3, and a threshold detecting circuit 5 which is constituted to detect the drop of the voltage Vcc and supplies a signal obtained as the function of variation between reset signals POR generated during the power supply rising period of the storage device 1 to the logic circuit 3.
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Patent Agency Ranking
公开(公告)号：JPH07249296A
公开(公告)日：1995-09-26
申请号：JP11795
申请日：1995-01-04
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , OLIVO MARCO , GOLLA CARLA
Abstract: PURPOSE: To improve a stability of tripping threshold value of an output signal and operating range controllability by providing a threshold value detection circuit for detecting a low threshold voltage without being affected by the change of a reference voltage. CONSTITUTION: A comparator 3 has a stable reference voltage RIF to be held at an input terminal regardless of supply voltage and temperature. By using this stable voltage reference, the tripping threshold value of the comparator 3 can be exactly set. In a normal operating state, an output signal VCCLOW from the comparator 3 is zero but when a supply voltage Vdd is reduced lower than a tripping level or a concerned circuit is turned into about 2.5V or deep power down state, for example, the voltage is increased to a voltage value Vu on a power supply line 2. Respective elements are provided with MOS transistors to be controlled by a signal PWDN according to the negative logic obtained from the external signal PWD through a negator N1. Thus, the stability of the tripping threshold value and the operation controllability can be improved.
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公开(公告)号：DE69427686D1
公开(公告)日：2001-08-16
申请号：DE69427686
申请日：1994-03-31
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , MACCARRONE MARCO , OLIVO MARCO
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公开(公告)号：DE69325458T2
公开(公告)日：1999-10-21
申请号：DE69325458
申请日：1993-12-31
Applicant: ST MICROELECTRONICS SRL
Inventor： OLIVO MARCO , PADOAN SILVIA
Abstract: A method for generating a reset signal in an electrically programmable non-volatile storage device (1) of a type which comprises a matrix (2) of memory cells and a control logic portion (3) being supplied a supply voltage (Vcc) and a programming voltage (Vpp), and a threshold detection circuit (5) adapted to detect a decrease in the supply voltage (Vcc), provides for the signal applied to the control logic (3) to be obtained as a change-over function between the output signal from the threshold detector (5) and a reset signal (POR) generated during the power-on transient of the device.
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公开(公告)号：DE69428423T2
公开(公告)日：2002-06-20
申请号：DE69428423
申请日：1994-02-21
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , PADOAN SILVIA , OLIVO MARCO
Abstract: A regulating circuit for discharging non-volatile memory cells (5) in an electrically programmable memory device, of the type which comprises: at least one switch connected between a programming voltage reference (VPP) and a line (SCR) shared by the source terminals of the transistors forming said memory cells (5), and at least one discharge connection between said common line (SCR) to the source terminals and a ground voltage reference (GND), further comprises a second connection to ground of the line (SCR) in which a current (Is) generator (G) is connected and a normally open switch (I1). Also provided is a logic circuit (3) connected to the line (SRC) to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch (I1) to make. This solution allows a slow discharging phase of the line (SRC) to be effected at the end of the erasing phase.
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公开(公告)号：DE69427686T2
公开(公告)日：2002-04-25
申请号：DE69427686
申请日：1994-03-31
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , MACCARRONE MARCO , OLIVO MARCO
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