公开(公告)号：JPH0863953A

公开(公告)日：1996-03-08

申请号：JP4930295

申请日：1995-02-15

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

IPC: G11C17/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

Abstract: PURPOSE: To obtain a load signal generating method and circuit for a non- volatile memory. CONSTITUTION: A circuit 1 is used to generate a variable length data load pulse L depending on the requirement and is provided with a source 5 for applying a short load signal SP and a delay element 19 for generating a long pulse STP when the short load signal appears. Static operation mode is given so that a load pulse is generated continuously through the static operation so long as the critical state (standby condition, low voltage) is continued. An expanded pulse is always generated when the static operation mode terminates, while a delay element 19 is disabled by a command EN when the expanded timing is not required.

公开(公告)号：JP2589458B2

公开(公告)日：1997-03-12

申请号：JP30221994

申请日：1994-12-06

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

IPC: H01L21/82 ,  G11C29/00 ,  H01L27/10

公开(公告)号：JP2588692B2

公开(公告)日：1997-03-05

申请号：JP2664295

申请日：1995-02-15

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

公开(公告)号：JPH0896569A

公开(公告)日：1996-04-12

申请号：JP5038495

申请日：1995-02-16

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO ,  GOLLA CARLA MARIA

IPC: G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

Abstract: PURPOSE: To obtain an internal timing method to a rewritable memory and a circuit thereof. CONSTITUTION: A circuit 1 generates slow or fast overall timing configuration and flexible timing enabling the two configuration of pre-charge and detection intervals by giving the levels of two short and long periods. For conduct the generation of the timing, variable asymmetric propagation lines 5, 37 consisting of a series of basic delay elements 6-8, 38, 40 bringing data to an enable or disenable state on the basis of logical signals TIMS, PCS, and DETS stored are contained in the circuit 1, and the state is determined when a memory 100 executed by the circuit is debugged.

公开(公告)号：JPH0883494A

公开(公告)日：1996-03-26

申请号：JP5377795

申请日：1995-02-20

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C17/00

Abstract: PURPOSE: To obtain a timer which can be constituted by a slow element excellent in noise characteristics. CONSTITUTION: This embodiment is a nonvolatile memory 100 comprising a data amplifier 106 and an output element 108 connecting with each other via a connection line 107. A noise suppression circuit 1 comprises networks 8, 18 for generating a noise suppression signal N which is synchronized completely with a signal L for controlling a data loading from the amplifier 106 to the output device 108. A very short lasting time period same as a switch time period of the output device 108 is given, and when the output device 108 is switched, the amplifier 106 is frozen, and data stored in the amplifier or an internal circuit of the memory 100 cannot be changed. An address amplifier 102 on address buses 101, 103 is blockaded according to the same signal.

公开(公告)号：JPH0847246A

公开(公告)日：1996-02-16

申请号：JP1306395

申请日：1995-01-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  PADOAN SILVIA

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H02M3/07

Abstract: PURPOSE: To supply large power in the case that an input/output voltage ratio is low or a power supply voltage is low by mutually connecting in parallel pull-up stages between a reference potential line and an output line. CONSTITUTION: This charge pump circuit 1 is provided with numerous stages 21 -2n connected in parallel to each other between the reference potential line 3 and the output line 4, the respective stages 21 -2n are provided with bootstrap capacitors 51 -5n , the one side is connected to nodes 71 -7n and the other terminals are connected to nodes 61 -6n . Then, when inverters 121 -12n are switched, the odd-numbered stages 21 , 23 ,... are switched to a charge transfer mode, the even- numbered stages are switched to a charging mode. When a switching edge reaches a stage 2n-1 which is one next to the last, an AND circuit 15 and a NOR circuit 16 are switched, shifting along the inverters 121 -12n is performed, the odd-numbered stages 21 , 23 ,... are charged, and the even-numbered stages 22 , 24 ,... transfer the stored charges. As a result, even in the case that an input voltage ratio is low, voltage is efficiently boosted and a large power is supplied.

公开(公告)号：JPH0845289A

公开(公告)日：1996-02-16

申请号：JP5377695

申请日：1995-02-20

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

Abstract: PURPOSE: To set a timing accurately while suppressing noise by loading a simulate signal to an output simulation circuit through a switch subjected to required control and resetting a simulate generation circuit in response to the variation of simulate signal. CONSTITUTION: Upon provision of a sync signal SYNC, a simulate signal SP is generated from the simulate signal generator 34 of delay FF and a load block signal SS makes a transition to L through a switch 35 opened by a load enable signal L before being loaded to an unblocked output simulation circuit 21. When the signal SP is inverted to 'L', output is inverted to H through a NAND gate 30 and an inverter 32 and the generator 34 is reset instantaneously through a monostable multivibrator 33. On the other hand, a signal SS is inverted to H and loading to the circuit 21 is blocked. According to the circuitry, loading of signal and blocking of loading are controlled accurately and the effect of noise due to housing is suppressed.

公开(公告)号：JPH07262792A

公开(公告)日：1995-10-13

申请号：JP30221994

申请日：1994-12-06

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

IPC: H01L21/82 ,  G11C29/00 ,  H01L27/10

Abstract: PURPOSE: To reduce a chip area by unnecessitating any protection memory cell by forming a combined circuit for generating a signal for inhibiting the selection of any memory cell. CONSTITUTION: A non-volatile register 1 is formed from memory cells MC0-MCn and a redundant word line selection circuit 2. The cells MC0-MCn have output signals CMP0-CMPn to be activated when row address signals are coincident with memories. The selection circuit 2 inputs all the signals CM0-CMPn and generates signals RS0-RSi for selecting any one redundant line word and preventing the defective word line of which the address is coincident with the address stored in the register from being selected. Besides, a combined circuit 3 generates a signal DIS for inhibiting the selection circuit 2 from generating the signals RS0-RSi. The protection memory cell is unnecessitated by a redundant circuit formed from the selection circuit 2 and the combined circuit 3.

公开(公告)号：JPH07254296A

公开(公告)日：1995-10-03

申请号：JP30490094

申请日：1994-12-08

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO

IPC: G11C29/00 ,  G11C29/04

Abstract: PURPOSE: To provide an integrated circuit for checking the use rate of a redundant memory element inside a semiconductor memory device. CONSTITUTION: A redundant circuit is provided with a programmable nonvolatile memory register 1 for respectively storing the addresses of defective memory elements. When the stored address is coincident with supplied address signals A0-An, a redundant select signal RS is generated. Besides, the signals A0-A1 are supplied to combined circuit means 3 and 9 of the redundant circuit and when a suppress signal DIS' is supplied to the register 1 and the signals A0-An are coincident with the addresses stored in the non-programmed register 1, the generation of the redundant select signal RS is suppressed. When a control signal CHKN is activated, a multiplexer circuit means 11 under the control of the signal CHKN transmits the signal RS to and output pad 17 and when the generation of the signal DIS' is activated, the signal CHKN disturbs that generation.

公开(公告)号：JPH06325592A

公开(公告)日：1994-11-25

申请号：JP5878794

申请日：1994-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： OLIVO MARCO ,  PASCUCCI LUIGI

IPC: G11C29/00 ,  G11C11/00 ,  G11C29/04

Abstract: PURPOSE: To unnecessitate a specified load circuit to program cells in a redundancy row by positioning at an intersection a line and a row of matrix itself and providing matrix consisting of memory cells. CONSTITUTION: A load circuit 3 for programming is connected to a common drain of transistors MS and MSR of each bucket 1. The circuit 3 consists of P channel MOS type transistor MP1, its drain is connected to the common drain of the transistors MS and MSR, its source is connected to programming voltage VP and its gate is connected to an input of a circuit 4 which has a NAND logic function. The circuit 4 is provided with a P channel MOS type load transistor M41, its source and drain are respectively connected to the voltage VP and a gate of the MP1 and make them ground electric potential. A drain of a transistor M42 is connected to a drain of the transistor M41, a drain of a transistor M43 is connected to its source, the source is ground electric potential and signals YMO to YM7 are given here. Thus, a signal DIN to program is acquired.