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    11.
    发明专利
    未知

    公开(公告)号：DE69806484D1

    公开(公告)日：2002-08-14

    申请号：DE69806484

    申请日：1998-11-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE ,  PINTO ANGELO

    IPC: H01L21/336 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8249 ,  H01L29/78

    Abstract: The following steps are performed on a wafer of semiconductor material having a layer (1) with n conductivity: a) implanting n impurity ions and p impurity ions in an area of the layer and subjecting the wafer to a high-temperature treatment; the impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first, p region (49) and a second, n region (50) which forms a pn junction with the first region (49); b) hollowing out a trench (43) which intersects the first region (49) and the second region (50), c) forming a dielectric coating (44) on the lateral surface of the trench (43), d) depositing electrically-conductive material (51) in the trench (43) in contact with the dielectric (44), and e) forming elements (60, 61, 62) for electrical contact with the layer (1), with the second region (50), and with the electrically-conductive material (51) inside the trench (43), in order to produce drain (D), source (S) and gate (G) electrodes of the MOSFET, respectively. A submicrometric vertical-channel MOSFET of optimal quality and reproducibility is thus produced by a method compatible with DPSA technology.

    12.
    发明专利
    未知

    公开(公告)号：ITTO20001100A1

    公开(公告)日：2002-05-24

    申请号：ITTO20001100

    申请日：2000-11-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE

    IPC: H01L21/02 ,  H01L27/08 ,  H01L29/8605

    Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity. In this way, either a resistive element presenting a substantially linear performance in all ranges of applied voltage or a resistive element presenting a marked increase of the resistance value as the applied voltage increases can be made. This all with the additional possibility of selectively varying the resistance value demonstrated before the increase.

    15.
    发明专利
    未知

    公开(公告)号：DE69935664D1

    公开(公告)日：2007-05-10

    申请号：DE69935664

    申请日：1999-06-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE ,  VALVO GIUSEPPINA

    IPC: H01L31/118 ,  H01L25/04 ,  H01L31/115

    Abstract: A particle detector formed in a chip of semiconductor material comprises: a first layer (42) with a first type of conductivity (n) having a surface on the first major surface of the chip, a second layer (40) with the first type of conductivity (n) having a surface on the second major surface of the chip, a third layer (41) with the first type of conductivity (n) having a resistivity lower than those of the first and second layers and disposed between the first layer (42) and the second layer (40), a first region (46) with a second type of conductivity (p), extending from the first surface into the first layer (42), a second region (45) with the second type of conductivity (p), extending from the second major surface into the second layer (40), and first (48), second (50,51) and third (43,47) electrical connection means for connection with the first region (46) with the second region (45), and with the third layer (41), respectively. To produce a position detector which does not require a large number of connections, the second electrical connection means comprise two electrodes (50,51) arranged a predetermined distance apart on the surface of the second region (45).

    16.
    发明专利
    未知

    公开(公告)号：ITVA20020034A1

    公开(公告)日：2003-11-17

    申请号：ITVA20020034

    申请日：2002-05-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： AIELLO NATALE ,  PATTI DAVIDE

    IPC: H01L27/06 ,  H01L29/94

    Abstract: A capacitor for sensing the substrate voltage is efficiently and economically realized simply by isolating a portion or segment of the metal layer that normally covers the heavily doped perimetral region of electric field equalization and, in correspondence of such a metal segment isolated by the remaining portion, by not removing preventively the isolation dielectric layer of silicon oxide from the surface of the semiconductor substrate, as it is normally done on the remaining portion of the perimetral edge region before depositing the metal. The unremoved layer of isolated silicon oxide (12) becomes the dielectric layer of the so constituted capacitor, a plate of which is the heavily doped perimetral region (4) that is electrically connected to the substrate (drain or collector region) while the other plate is constituted by the segment of metal (4'), isolated from the remaining metal layer defined directly over the heavily doped perimetral region (4).

    17.
    发明专利
    未知

    公开(公告)号：IT1309699B1

    公开(公告)日：2002-01-30

    申请号：ITMI990331

    申请日：1999-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE

    IPC: H01L27/07 ,  H01L29/73

    Abstract: The device is constituted by an N+ substrate, by an N- layer on the substrate, by a metal contact for a collector, by a buried P- base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on the base contact region for a base, by an N+ emitter region buried in the insulated region and forming a pn junction with the buried base region, by a P+ body region in the insulated region, by an N+ source region in the P+ region, by a metal contact for a source, and by a gate electrode. In order to achieve a low resistance Ron, the P+ body region extends as far as the buried N+ emitter region and an additional N+ region is provided within the body region and constitutes a drain region, defining, with the source region, the channel of a lateral MOSFET transistor.

    18.
    发明专利
    未知

    公开(公告)号：ITTO20000319A1

    公开(公告)日：2001-10-04

    申请号：ITTO20000319

    申请日：2000-04-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE ,  RONSISVALLE CESARE

    IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

    Abstract: A process for manufacturing deep well junction structures that includes in succession, the steps of: on a first substrate having a first conductivity type and a first doping level, growing an epitaxial layer having the first conductivity type and a second doping level lower than the first doping level; anisotropically etching the epitaxial layer using a mask to form trenches; forming deep conductive regions surrounding the trenches and having a second conductivity type, opposite to the first conductivity type and the second doping level; and filling the trenches. The deep conductive regions are formed by angular ionic implantation and subsequent diffusion of a doping ion species within the epitaxial layer.

    20.
    发明专利
    未知

    公开(公告)号：ITTO20001100D0

    公开(公告)日：2000-11-24

    申请号：ITTO20001100

    申请日：2000-11-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE

    IPC: H01L21/02 ,  H01L27/08 ,  H01L29/8605

    Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity. In this way, either a resistive element presenting a substantially linear performance in all ranges of applied voltage or a resistive element presenting a marked increase of the resistance value as the applied voltage increases can be made. This all with the additional possibility of selectively varying the resistance value demonstrated before the increase.

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