公开(公告)号：DE69723044T2

公开(公告)日：2004-05-06

申请号：DE69723044

申请日：1997-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CALEGARI CAMILLA ,  CARRARA ANNA ,  FRATIN LORENZO ,  RIVA CARLO

IPC: H01L23/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

Abstract: A process for the formation of a device edge morphological structure (30) for protecting and sealing peripherally an electronic circuit integrated in a major surface (5) of a substrate of semiconductor material (6) is of the type that calls for formation above the major surface (5) of at least one dielectric multilayer (20) comprising a layer of amorphous planarizing material (22) having a continuous portion extending between two contiguous areas with a more internal first area (3') and a more external second area (4') in the morphological structure (30). In accordance with the present invention inside the device edge morphological structure (30) in the substrate (6) is formed an excavation on the side of the major surface (5) the more internal first area (3') of the morphological structure (30) in a zone in which is present the continuous portion of the dielectric multilayer (20).

公开(公告)号：DE69528970D1

公开(公告)日：2003-01-09

申请号：DE69528970

申请日：1995-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CLEMENTI CESARE ,  GHIDINI GABRIELLA ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) having an intermediate dielectric multilayer including at least a lower dielectric material layer (8) and an upper silicon oxide layer (9) and the simultaneous provision in zones peripheral to the matrix of at least one first transistor type (2) having gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer (4) and a polycrystalline silicon layer (5) and the formation of the lower dielectric material layer (8), the process in accordance with the present invention calls for: removal of said layers from the peripheral zones (R2) of the matrix; deposition of said upper silicon oxide layer (9) over the memory cells (1),and over the substrate (3) in the areas (R2) of the peripheral transistors (2); and formation of a first silicon oxide layer (10) at least in the areas (R2) of the peripheral transistors (2). To provide additionally a second transistor type having gate dielectric of a second thickness, indicatively thinner than said first thickness, successive steps are added in accordance with the present invention.

公开(公告)号：DE69032937T2

公开(公告)日：1999-06-17

申请号：DE69032937

申请日：1990-07-24

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82 ,  G11C16/04

Abstract: The process provides for the simultaneous N+ type implantation of areas (7, 8, 9) of a semiconductor substrate of type P for the formation of a control gate (9) and of highly doped regions of source (7) and drain (8), defining a channel region (4). After oxide growth (11, 12) there is executed the deposition and the definition of a polysilicon layer (10), one region of which constitutes a floating gate above the control gate (9) and the channel region (4) and partially superimposed over the regions of source (7) and drain (8).

公开(公告)号：DE69413960D1

公开(公告)日：1998-11-19

申请号：DE69413960

申请日：1994-07-18

Applicant: ST MICROELECTRONICS SRL

Inventor： FRATIN LORENZO ,  RAVAZZI LEONARDO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  H01L21/00

Abstract: A nonvolatile memory (40) having a cell (31) comprising an N type source region (24) and drain region (12) embedded in a P type substrate (4) and surrounded by respective P-pockets (26, 16). The drain and source P-pockets (16, 26) are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell (31) also presents a higher breakdown voltage as compared with known cells.

公开(公告)号：DE69630944D1

公开(公告)日：2004-01-15

申请号：DE69630944

申请日：1996-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： FRATIN LORENZO ,  RIVA CARLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8247

Abstract: A MOS transistor (1) capable of withstanding relatively high voltages is of a type integrated on a region (3) included in a substrate of semiconductor material, having conductivity of a first type (N) and comprising a channel region (7) intermediate between a first active region of source (4) and a second active region of drain (5). Both these regions (4 and 5) have conductivity of a second type (P) and extend from a first surface (6) of the substrate. The transistor (1) also has a gate which comprises at least a first polysilicon layer (8) overlying the first surface (6) at at least said channel region (7), to which it is coupled capacitively through a gate oxide layer (9). According to the invention, the first polysilicon layer (8) includes a mid-portion (13) which only overlies said channel region (7) and has a first total conductivity (C1) of said first type (N), and a peripheral portion (14) with a second total conductivity (C2) differentiated from said first total conductivity (C1), which peripheral portion partly overlies said source and drain active regions (4 and 5) toward said channel region (7).

公开(公告)号：DE69624107T2

公开(公告)日：2003-06-05

申请号：DE69624107

申请日：1996-07-18

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A flash EEPROM memory cell comprises source and drain regions (71,72,81,82;73,83) defining a channel region therebetween, a floating gate (10) and a control gate (9). The source and drain regions are first and second doped semiconductor regions (71,72,81,82;73,83) of a first conductivity type formed in a first active area region (33) of a semiconductor material layer (1) of a second conductivity type; the control gate comprises a third doped semiconductor region (9) of the first conductivity type formed in a second active area region (34) of the semiconductor material layer (1); and the floating gate comprises a polysilicon strip (10) insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region (9).

公开(公告)号：DE69624107D1

公开(公告)日：2002-11-07

申请号：DE69624107

申请日：1996-07-18

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A flash EEPROM memory cell comprises source and drain regions (71,72,81,82;73,83) defining a channel region therebetween, a floating gate (10) and a control gate (9). The source and drain regions are first and second doped semiconductor regions (71,72,81,82;73,83) of a first conductivity type formed in a first active area region (33) of a semiconductor material layer (1) of a second conductivity type; the control gate comprises a third doped semiconductor region (9) of the first conductivity type formed in a second active area region (34) of the semiconductor material layer (1); and the floating gate comprises a polysilicon strip (10) insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region (9).

公开(公告)号：DE69330401T2

公开(公告)日：2002-06-06

申请号：DE69330401

申请日：1993-02-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/115 ,  G11C16/04 ,  H01L29/788

公开(公告)号：DE69330401D1

公开(公告)日：2001-08-09

申请号：DE69330401

申请日：1993-02-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/115 ,  G11C16/04 ,  H01L29/788

公开(公告)号：DE69413960T2

公开(公告)日：1999-04-01

申请号：DE69413960

申请日：1994-07-18

Applicant: ST MICROELECTRONICS SRL

Inventor： FRATIN LORENZO ,  RAVAZZI LEONARDO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  H01L21/00

Abstract: A nonvolatile memory (40) having a cell (31) comprising an N type source region (24) and drain region (12) embedded in a P type substrate (4) and surrounded by respective P-pockets (26, 16). The drain and source P-pockets (16, 26) are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell (31) also presents a higher breakdown voltage as compared with known cells.