公开(公告)号：DE69631657D1

公开(公告)日：2004-04-01

申请号：DE69631657

申请日：1996-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  ROLANDI PIER LUIGI ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  SABATINI MARCO

IPC: G06G7/26 ,  G06N3/063 ,  G11C16/04 ,  G06G7/60

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors (M1,M2) having source and drain terminals which are coupled together and to an injection node (ND), and at least one corresponding pair of generators (G1,G2) of substantially step-like voltage signals (S1,S2) having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors (M1,M2); the signal generators (G1,G2) being such that the initial value of a first (S1) of the signals is substantially the equal of the final value of a second (S2) of the signals, and that the final value of the first signal (S1) is substantially the equal of the initial value of the second signal (S2).

公开(公告)号：DE69628753D1

公开(公告)日：2003-07-24

申请号：DE69628753

申请日：1996-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

IPC: G11C15/00 ,  G11C15/04

Abstract: An input structure (1) for associative memories, including an array of elementary cells (2), a number of input lines (20), a number of output lines (30), a number of address lines (40), and a number of enabling lines (50). Each elementary cell (2) is formed by a D type latch (3) having a data input connected to one of the address lines (40) and an enabling input connected to one of the enabling lines (50), and by a switch (4) connected between an input line and an output line, and having a control input connected to the output of a respective latch to selectively connect the respective input line (20) and output line (30) according to the data stored in the latch.

公开(公告)号：DE69314964T2

公开(公告)日：1998-06-04

申请号：DE69314964

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： KRAMER ALAN ,  SABATINI MARCO

IPC: H01L21/8247 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  G11C27/00

Abstract: Non-volatile memory cell with double level of polycrystalline silicon comprising a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) in which the channel region area extends into two lateral zones beneath the two gates and perpendicular to the source-drain direction.