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    NONVOLATILE MEMORY AND CELL
    2.
    发明专利
    NONVOLATILE MEMORY AND CELL 失效

    公开(公告)号：JPH07326680A

    公开(公告)日：1995-12-12

    申请号：JP32565594

    申请日：1994-12-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  SABATINI MARCO

    IPC: H01L21/8247 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

    Abstract: PURPOSE: To obtain a very small sized capacitive element which has a nonlinear characteristic and is capable of programming in an analog mode. CONSTITUTION: A flash EEPROM memory cell 30 is a nonvolatile memory cell includes a 2 level polycrystalline silicon, and a source region 38, a drain region 31, a channel region 34 between the source region and the drain region, a floating gate 33, and a control gate 32, the channel region extending to two transversal zone below the floating gate and the control gate and perpendicularly to a source/drain direction.

    4.
    发明专利
    未知

    公开(公告)号：DE69628165D1

    公开(公告)日：2003-06-18

    申请号：DE69628165

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  LEONG PHILIP ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

    IPC: H03M1/74

    Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals and an output (OUT) for an analog signal, and comprising a current amplification circuit (AMP) having an input (ND) and an output coupled to the converter output; and a plurality of floating gate MOS transistors (M01, M11, M21, M31) corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference (GND) of potential, drain terminals coupled together and to the input (ND) of the amplification circuit (AMP), and control terminals coupleable, under control from the inputs of the plurality, to different references (GND,VCC) of potential having selected fixed values.

    10.
    发明专利
    未知

    公开(公告)号：DE69314964D1

    公开(公告)日：1997-12-04

    申请号：DE69314964

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  SABATINI MARCO

    IPC: H01L21/8247 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  G11C27/00

    Abstract: Non-volatile memory cell with double level of polycrystalline silicon comprising a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) in which the channel region area extends into two lateral zones beneath the two gates and perpendicular to the source-drain direction.

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