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    NONVOLATILE MEMORY AND CELL
    1.
    发明专利
    NONVOLATILE MEMORY AND CELL 失效

    公开(公告)号：JPH07326680A

    公开(公告)日：1995-12-12

    申请号：JP32565594

    申请日：1994-12-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  SABATINI MARCO

    IPC: H01L21/8247 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

    Abstract: PURPOSE: To obtain a very small sized capacitive element which has a nonlinear characteristic and is capable of programming in an analog mode. CONSTITUTION: A flash EEPROM memory cell 30 is a nonvolatile memory cell includes a 2 level polycrystalline silicon, and a source region 38, a drain region 31, a channel region 34 between the source region and the drain region, a floating gate 33, and a control gate 32, the channel region extending to two transversal zone below the floating gate and the control gate and perpendicularly to a source/drain direction.

    4.
    发明专利
    未知

    公开(公告)号：DE69705478D1

    公开(公告)日：2001-08-09

    申请号：DE69705478

    申请日：1997-10-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVIERI MASSIMILIANO ,  FABBRIZIO VITO ,  GUERRIERI ROBERTO ,  KRAMER ALAN

    IPC: G06T1/00 ,  G05D1/02 ,  G06T7/60 ,  G05B1/03 ,  G05D1/03

    Abstract: Method (10), in a system for aiding the guidance of a vehicle, for identifying marking stripes of road lanes comprising the phases of subjecting a road image to a convolution operation (14) with a mask matrix so as to identify discontinuities present in the image, comparing the result with a threshold value (16) and determining (18) a representation of the marking stripes, in which the mask matrix is set in such a way as to eliminate at least partially the discontinuities which do not correspond to the marking stripes.

    5.
    发明专利
    未知

    公开(公告)号：DE69518326T2

    公开(公告)日：2001-01-18

    申请号：DE69518326

    申请日：1995-10-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FABBRIZIO VITO ,  COLLI GIANLUCA ,  KRAMER ALAN

    IPC: G06G7/60 ,  G06F15/18 ,  G06N3/06 ,  G06N3/063 ,  G06F15/80

    Abstract: A neural network (1) including a number of synaptic weighting elements (15, 17), and a neuron stage (5); each of the synaptic weighting elements (15, 17) having a respective synaptic input connection (11, 13) supplied with a respective input signal (x1, ..., xn); and the neuron stage (5) having inputs (36, 37) connected to the synaptic weighting elements, and being connected to an output (39) of the neural network (1) supplying a digital output signal (O). The synaptic weighting elements (15, 17) are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage (5) provides for measuring conductance (33-35, 43-45) on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

    6.
    发明专利
    未知

    公开(公告)号：DE69631657D1

    公开(公告)日：2004-04-01

    申请号：DE69631657

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  ROLANDI PIER LUIGI ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  SABATINI MARCO

    IPC: G06G7/26 ,  G06N3/063 ,  G11C16/04 ,  G06G7/60

    Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors (M1,M2) having source and drain terminals which are coupled together and to an injection node (ND), and at least one corresponding pair of generators (G1,G2) of substantially step-like voltage signals (S1,S2) having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors (M1,M2); the signal generators (G1,G2) being such that the initial value of a first (S1) of the signals is substantially the equal of the final value of a second (S2) of the signals, and that the final value of the first signal (S1) is substantially the equal of the initial value of the second signal (S2).

    7.
    发明专利
    未知

    公开(公告)号：DE69628753D1

    公开(公告)日：2003-07-24

    申请号：DE69628753

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

    IPC: G11C15/00 ,  G11C15/04

    Abstract: An input structure (1) for associative memories, including an array of elementary cells (2), a number of input lines (20), a number of output lines (30), a number of address lines (40), and a number of enabling lines (50). Each elementary cell (2) is formed by a D type latch (3) having a data input connected to one of the address lines (40) and an enabling input connected to one of the enabling lines (50), and by a switch (4) connected between an input line and an output line, and having a control input connected to the output of a respective latch to selectively connect the respective input line (20) and output line (30) according to the data stored in the latch.

    8.
    发明专利
    未知

    公开(公告)号：DE69314964T2

    公开(公告)日：1998-06-04

    申请号：DE69314964

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  SABATINI MARCO

    IPC: H01L21/8247 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  G11C27/00

    Abstract: Non-volatile memory cell with double level of polycrystalline silicon comprising a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) in which the channel region area extends into two lateral zones beneath the two gates and perpendicular to the source-drain direction.

    9.
    发明专利
    未知

    公开(公告)号：DE69518326D1

    公开(公告)日：2000-09-14

    申请号：DE69518326

    申请日：1995-10-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FABBRIZIO VITO ,  COLLI GIANLUCA ,  KRAMER ALAN

    IPC: G06G7/60 ,  G06F15/18 ,  G06N3/06 ,  G06N3/063 ,  G06F15/80

    Abstract: A neural network (1) including a number of synaptic weighting elements (15, 17), and a neuron stage (5); each of the synaptic weighting elements (15, 17) having a respective synaptic input connection (11, 13) supplied with a respective input signal (x1, ..., xn); and the neuron stage (5) having inputs (36, 37) connected to the synaptic weighting elements, and being connected to an output (39) of the neural network (1) supplying a digital output signal (O). The synaptic weighting elements (15, 17) are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage (5) provides for measuring conductance (33-35, 43-45) on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

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