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    3.
    发明专利
    未知

    公开(公告)号：DE69631657D1

    公开(公告)日：2004-04-01

    申请号：DE69631657

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  ROLANDI PIER LUIGI ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  SABATINI MARCO

    IPC: G06G7/26 ,  G06N3/063 ,  G11C16/04 ,  G06G7/60

    Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors (M1,M2) having source and drain terminals which are coupled together and to an injection node (ND), and at least one corresponding pair of generators (G1,G2) of substantially step-like voltage signals (S1,S2) having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors (M1,M2); the signal generators (G1,G2) being such that the initial value of a first (S1) of the signals is substantially the equal of the final value of a second (S2) of the signals, and that the final value of the first signal (S1) is substantially the equal of the initial value of the second signal (S2).

    4.
    发明专利
    未知

    公开(公告)号：DE69628753D1

    公开(公告)日：2003-07-24

    申请号：DE69628753

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

    IPC: G11C15/00 ,  G11C15/04

    Abstract: An input structure (1) for associative memories, including an array of elementary cells (2), a number of input lines (20), a number of output lines (30), a number of address lines (40), and a number of enabling lines (50). Each elementary cell (2) is formed by a D type latch (3) having a data input connected to one of the address lines (40) and an enabling input connected to one of the enabling lines (50), and by a switch (4) connected between an input line and an output line, and having a control input connected to the output of a respective latch to selectively connect the respective input line (20) and output line (30) according to the data stored in the latch.

    6.
    发明专利
    未知

    公开(公告)号：DE69628165D1

    公开(公告)日：2003-06-18

    申请号：DE69628165

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  LEONG PHILIP ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

    IPC: H03M1/74

    Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals and an output (OUT) for an analog signal, and comprising a current amplification circuit (AMP) having an input (ND) and an output coupled to the converter output; and a plurality of floating gate MOS transistors (M01, M11, M21, M31) corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference (GND) of potential, drain terminals coupled together and to the input (ND) of the amplification circuit (AMP), and control terminals coupleable, under control from the inputs of the plurality, to different references (GND,VCC) of potential having selected fixed values.

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