公开(公告)号：ITMI992350D0

公开(公告)日：1999-11-10

申请号：ITMI992350

申请日：1999-11-10

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115

Abstract: A process for selectively sealing ferroelectric capacitive elements in non-volatile memory cells being integrated in a semiconductor substrate and comprising at least one MOS transistor, which process comprises at least the following steps: forming said at least one MOS transistor on the semiconductor substrate, and depositing an insulating layer over the whole surface of the semiconductor; and further comprises the steps of: depositing a first metal layer to form, using a photolithographic technique, a lower electrode of at least one ferroelectric capacitive element; depositing a layer of a dielectric material onto said first layer; depositing a second metal layer to form, using a photolithographic technique, an upper electrode of at least one ferroelectric capacitive element; depositing a layer of a sealing material onto said second metal layer; defining the dielectric material layer and sealing layer by a single photolithographic defining step, so as to pattern said dielectric layer and concurrently seal said at least one capacitive element.

公开(公告)号：DE69631524T2

公开(公告)日：2004-10-07

申请号：DE69631524

申请日：1996-07-05

Applicant: ST MICROELECTRONICS SRL

Inventor： MAGRI ANGELO ,  ZAMBRANO RAFFAELE ,  FRISINA FERRUCCIO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

公开(公告)号：ITTO20020118A1

公开(公告)日：2003-08-08

申请号：ITTO20020118

申请日：2002-02-08

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: G11C11/00

Abstract: An integrated device including a first memory array having first memory cells of a nonvolatile type and a second memory array having second memory cells of a volatile type (DRAM). The first memory cells and the second memory cells are formed in a substrate of semiconductor material, and each includes a respective MOS transistor which is formed in an active region of the substrate and has a first conductive region and a respective capacitor which is formed on top of the active region and has a first electrode and a second electrode, which are separated by a dielectric region. Moreover, the first electrode of the capacitor is connected to the first conductive region of the MOS transistor. The first and the second memory cells have a structure that is substantially the same and are formed simultaneously.

公开(公告)号：IT1314025B1

公开(公告)日：2002-12-03

申请号：ITMI992350

申请日：1999-11-10

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115

Abstract: A process for selectively sealing ferroelectric capacitive elements in non-volatile memory cells being integrated in a semiconductor substrate and comprising at least one MOS transistor, which process comprises at least the following steps: forming said at least one MOS transistor on the semiconductor substrate, and depositing an insulating layer over the whole surface of the semiconductor; and further comprises the steps of: depositing a first metal layer to form, using a photolithographic technique, a lower electrode of at least one ferroelectric capacitive element; depositing a layer of a dielectric material onto said first layer; depositing a second metal layer to form, using a photolithographic technique, an upper electrode of at least one ferroelectric capacitive element; depositing a layer of a sealing material onto said second metal layer; defining the dielectric material layer and sealing layer by a single photolithographic defining step, so as to pattern said dielectric layer and concurrently seal said at least one capacitive element.

公开(公告)号：ITTO20020118D0

公开(公告)日：2002-02-08

申请号：ITTO20020118

申请日：2002-02-08

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: G11C11/00

Abstract: An integrated device including a first memory array having first memory cells of a nonvolatile type and a second memory array having second memory cells of a volatile type (DRAM). The first memory cells and the second memory cells are formed in a substrate of semiconductor material, and each includes a respective MOS transistor which is formed in an active region of the substrate and has a first conductive region and a respective capacitor which is formed on top of the active region and has a first electrode and a second electrode, which are separated by a dielectric region. Moreover, the first electrode of the capacitor is connected to the first conductive region of the MOS transistor. The first and the second memory cells have a structure that is substantially the same and are formed simultaneously.

公开(公告)号：ITTO20000543A1

公开(公告)日：2001-12-06

申请号：ITTO20000543

申请日：2000-06-06

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: G11C17/12

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular P-. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.

公开(公告)号：DE69426565T2

公开(公告)日：2001-05-31

申请号：DE69426565

申请日：1994-09-21

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： PALARA SERGIO ,  ZAMBRANO RAFFAELE

IPC: H01L27/04 ,  H01L27/02 ,  H01L29/78 ,  H03K17/08 ,  H03K17/687

公开(公告)号：ITTO20000543D0

公开(公告)日：2000-06-06

申请号：ITTO20000543

申请日：2000-06-06

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: G11C17/12

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular P-. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.

公开(公告)号：ITTO990356D0

公开(公告)日：1999-04-30

申请号：ITTO990356

申请日：1999-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CORVASCE CHIARA ,  ZAMBRANO RAFFAELE

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material. In this way, the manufacturing process is not critical and the size of the cells is minimal.

公开(公告)号：DE69940422D1

公开(公告)日：2009-04-02

申请号：DE69940422

申请日：1999-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/20 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

Abstract: A process for manufacturing circuit structures (20,200) of the SOI type integrated on a semiconductor substrate (1,101) having a first type of conductivity, which process comprises the following steps: forming at least one well (2) with a second type of conductivity in said semiconductor substrate (1); forming a hole (4) in said at least one well (2); coating the hole (4) with an insulating coating layer (5); forming an opening (6) through the insulating coating layer (5) at the bottom of the hole (4); filling the hole with an epitaxial layer (7) grown from a seed made accessible through said opening (6).