公开(公告)号：EP1505656A1

公开(公告)日：2005-02-09

申请号：EP03425536.4

申请日：2003-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Bez, Roberto

IPC: H01L27/24

CPC classification number: H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells (33), arranged in rows and columns; and forming a plurality of resistive bit lines (35) for connecting PCM cells (33) arranged on a same column, each resistive bit lines (35) comprising a respective phase change material portion (31'), covered by a respective barrier portion (32'). After forming the resistive bit lines (35), electrical connection structures (45, 52) for the resistive bit lines (35) are formed directly in contact with the barrier portions (32') of the resistive bit lines (35).

Abstract translation: 一种用于制造相变存储器阵列的方法，包括以下步骤：形成PCM单元的多个（33），以行和列布置; 以及形成电阻的位线用于连接PCM单元布置在同一列有多个（35）（33），每个电阻的位线（35），其包括respectivement相变材料部分（31“）中，由一个respectivement阻挡部分覆盖（ 32“）。 形成用于电阻的位线电阻的位线（35），电连接结构（45，52）之后，（35）直接与所述电阻的位线（35）的阻挡部分（32“）接触而形成。

公开(公告)号：EP1306852A2

公开(公告)日：2003-05-02

申请号：EP02078984.8

申请日：2002-09-27

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Casagrande, Giulio ,  Lowrey, Tyler ,  Bez, Roberto ,  Wicker, Guy ,  Spall, Edward ,  Hudgens, Stephen ,  Czubatyj, Wolodymyr

IPC: G11C11/34

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

Abstract: A memory device (100) including a plurality of memory cells (M h,k ), a plurality of insulated first regions (220 h ) of a first type of conductivity formed in a chip of semiconductor material (203), at least one second region (230 k ) of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element (D h,k ) for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact (225 h ) for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements (D h,k ,D h,k+1 ) without interposition of any contact, and the memory device further includes means (110c,113,125) for forward biasing the access elements of each sub-set simultaneously.

Abstract translation: 一种存储器件（100），包括多个存储器单元（Mh，k），在半导体材料（203）的芯片中形成的具有第一导电类型的多个绝缘第一区域（220h），至少一个第二区域 在每个第一区域中形成的第二导电类型的第二区域，每个第二区域和对应的第一区域之间的接点限定单向导通入元件（D h，k），用于当正向偏置时选择连接到第二区域的相应存储单元 以及用于接触每个第一区域的至少一个触点（225h） 在每个第一区域中形成多个存取元件，所述存取元件在不插入任何接触的情况下被分组成至少一个由多个相邻存取元件（Dh，k，Dh，k + 1）组成的子集，以及 该存储设备还包括用于同时正向偏置每个子集的访问元件的装置（110c，113,125）。

公开(公告)号：EP1439579B1

公开(公告)日：2010-03-10

申请号：EP03425017.5

申请日：2003-01-15

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

IPC: H01L21/8238 ,  H01L27/24

CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

公开(公告)号：EP1729355A1

公开(公告)日：2006-12-06

申请号：EP05104879.1

申请日：2005-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Varesi, Enrico ,  Pirovano, Agostino ,  Petruzza, Pietro

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.

Abstract translation: 用于制造相变存储单元的方法包括在半导体晶片（10）中形成加热元件（25a）和在与加热器元件（25a）接触并与之接触的相变材料的存储区域（31a）的步骤。 为了形成加热器元件（25a）和相变储存区域（31a），首先形成加热器结构，并且相变层（31）沉积在加热器结构上并与加热器结构接触。 然后，通过随后的自对准蚀刻步骤限定相变层（31）和加热器结构。

公开(公告)号：EP0772246B1

公开(公告)日：2005-10-12

申请号：EP95830459.4

申请日：1995-10-31

Applicant: STMicroelectronics S.r.l.

Inventor： Bez, Roberto ,  Camerlenghi, Emilio

IPC: H01L21/02 ,  H01L29/92 ,  H01L29/94

CPC classification number: H01L28/40 ,  H01L29/94

公开(公告)号：EP1519489A1

公开(公告)日：2005-03-30

申请号：EP03021455.5

申请日：2003-09-23

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  De Sandre, Guido ,  Bez, Roberto

IPC: H03K19/177

CPC classification number: G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

Abstract: The present invention proposes a Field Programmable Gate Array (FPGA) device (100) comprising a plurality of configurable electrical connections (115 1 -115 2 ,115 1 -115 3 ), a plurality of controlled switches (205), each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit (125) including an arrangement of a plurality of control cells (200). Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element (210,215) adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element (P1;F1) coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

Abstract translation: 本发明提出了一种包括多个可配置电连接（1151-1152,1151-1153）的现场可编程门阵列（FPGA）装置，多个受控开关（205），每个控制开关适于启动/ 响应于开关控制信号激活至少一个相应的电连接，以及包括多个控制单元（200）的布置的控制单元（125）。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件（210,215），其适于以易失性方式存储对应于至少一个 控制开关，并且向控制开关提供与存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件（P1; F1），非易失性存储元件适于以非易失性方式存储控制逻辑值。

公开(公告)号：EP1306852A3

公开(公告)日：2004-03-10

申请号：EP02078984.8

申请日：2002-09-27

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Casagrande, Giulio ,  Lowrey, Tyler ,  Bez, Roberto ,  Wicker, Guy ,  Spall, Edward ,  Hudgens, Stephen ,  Czubatyj, Wolodymyr

IPC: G11C11/34 ,  G11C16/02

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

Abstract: A memory device (100) including a plurality of memory cells (M h,k ), a plurality of insulated first regions (220 h ) of a first type of conductivity formed in a chip of semiconductor material (203), at least one second region (230 k ) of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element (D h,k ) for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact (225 h ) for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements (D h,k ,D h,k+1 ) without interposition of any contact, and the memory device further includes means (110c,113,125) for forward biasing the access elements of each sub-set simultaneously.

公开(公告)号：EP1339103A1

公开(公告)日：2003-08-27

申请号：EP02425088.8

申请日：2002-02-20

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Casagrande, Giulio ,  Bez, Roberto ,  Pellizzer, Fabio

IPC: H01L23/522 ,  H01L23/528 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: An electronic semiconductor device has a sublithographic contact area (45, 58) between a first conductive region (22) and a second conductive region (38). The first conductive region (22) is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area (45, 58). The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract translation: 一种电子半导体器件具有第一导电区（22）和一个第二导电区（38）之间的亚光刻的接触面积（45，58）。 第一导电区（22）是杯形，并具有垂直壁延伸，在俯视图中，沿着细长形状的封闭线。 一个第一导电区域的壁的形成第一薄壁部，并且具有在第一方向上的第一尺寸。 第二导电区域（38）具有在第二方向上的第二亚光刻尺寸（X）横向于第一尺寸的第二薄壁部（38A）。 所述第一和第二导电区域在其薄的部分直接电接触，并形成亚光刻接触区域（45，58）。 细长形状在第一方向上的矩形和椭圆形的细长之间选择。 因此，接触区域的尺寸，即使在掩模之间的小的未对准的存在保持大致恒定，限定导电区域。

公开(公告)号：EP1179839A2

公开(公告)日：2002-02-13

申请号：EP01114948.1

申请日：2001-06-20

Applicant: STMicroelectronics S.r.l.

Inventor： Bez, Roberto ,  Camerlenghi, Emilio ,  Ratti Stefano

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps:

forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2);
cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell;
filling the at least one trench (6) with an isolation layer (7);
depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and
etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

公开(公告)号：EP1811564B1

公开(公告)日：2010-03-10

申请号：EP06425025.1

申请日：2006-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Tortorelli, Innocenzo ,  Pirovano, Agostino ,  Bez, Roberto

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/525 ,  G11C17/16

CPC classification number: H01L23/5256 ,  G11C13/0004 ,  G11C17/16 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00