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    Self-aligned process for manufacturing phase change memory cells
    3.
    发明公开
    Self-aligned process for manufacturing phase change memory cells 有权
    Selbstjustiertes Verfahren zur Herstellung von Phasenwechselspeicherzellen

    公开(公告)号：EP1729355A1

    公开(公告)日：2006-12-06

    申请号：EP05104879.1

    申请日：2005-06-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Varesi, Enrico ,  Pirovano, Agostino ,  Petruzza, Pietro

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.

    Abstract translation: 用于制造相变存储单元的方法包括在半导体晶片（10）中形成加热元件（25a）和在与加热器元件（25a）接触并与之接触的相变材料的存储区域（31a）的步骤。 为了形成加热器元件（25a）和相变储存区域（31a），首先形成加热器结构，并且相变层（31）沉积在加热器结构上并与加热器结构接触。 然后，通过随后的自对准蚀刻步骤限定相变层（31）和加热器结构。

    Phase change memory cell with diode junction selection and manufacturing method thereof
    4.
    发明公开
    Phase change memory cell with diode junction selection and manufacturing method thereof 审中-公开
    PhasenübergangsspeicherzellemitDiodenübergangsauswahlund Methode zu ihrer Herstellung

    公开(公告)号：EP1675183A1

    公开(公告)日：2006-06-28

    申请号：EP04425931.5

    申请日：2004-12-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Pirovano, Agostino

    IPC: H01L27/24

    CPC classification number: H01L27/2409 ,  G11C13/0016 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    Abstract: A memory cell (2) includes a memory element (3) and a selection element (30) coupled to said memory element (3). The selection element (30) includes a first junction portion (128a), having a first type of conductivity, and a second junction portion (128b), having a second type of conductivity and forming a rectifying junction (38) with the first junction portion (128a). The first junction portion (128a) and the second junction portion (128b) are made of materials selected in the group consisting of: chalcogenides and conducting polymers.

    Abstract translation: 存储单元（2）包括存储元件（3）和耦合到所述存储元件（3）的选择元件（30）。 选择元件（30）包括具有第一类型导电性的第一接合部分（128a）和具有第二类型导电性的第二接合部分（128b），并且与第一接合部分形成整流接头（38） （128A）。 第一接合部分（128a）和第二接合部分（128b）由选自以下的材料制成：硫族化物和导电聚合物。

    Phase change memory device for multibit storage
    5.
    发明公开
    Phase change memory device for multibit storage 有权
    Phasenwechsel-SpeichervorrichtungfürMultibit-Speicherung

    公开(公告)号：EP2034536A1

    公开(公告)日：2009-03-11

    申请号：EP07425555.5

    申请日：2007-09-07

    Applicant: STMicroelectronics S.r.l. ,  Politecnico di Milano

    Inventor： Redaelli, Andrea ,  Pellizzer, Fabio ,  Pirovano, Agostino

    IPC: H01L45/00

    CPC classification number: H01L45/1233 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144

    Abstract: A phase change memory device (10) having a heater element (2) and memory region (3) of chalcogenic material. The memory region has a phase changing portion (5) in electrical and thermal contact with the heater element and forms a first current path between the heater element and a rest portion (4) of the memory element. The phase changing portion (5) has a dimension correlated to information stored in the memory region and a higher resistivity than the rest portion (4). A parallel current path (11) extends between the heater element (2) and the rest portion (4) of said memory element and has a resistance depending upon the dimension of the phase changing portion (5) and lower than the phase changing portion (5), thus modulating the overall resistance of phase change memory device.

    Abstract translation: 具有加热器元件（2）和存储区域（3）的相变材料的相变存储器件（10）。 存储区域具有与加热器元件电接触和热接触的相变部分（5），并且在加热器元件和存储元件的其余部分（4）之间形成第一电流路径。 相位改变部分（5）具有与存储在存储区域中的信息相关的维度，并且比其余部分（4）具有更高的电阻率。 平行电流路径（11）在加热器元件（2）和所述存储元件的其余部分（4）之间延伸，并且具有取决于相变部分（5）的尺寸并且低于相变部分 5），从而调制相变存储器件的整体电阻。

    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions
    6.
    发明公开
    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions 审中-公开
    对于具有选择晶体管的双极单元阵列具有突出的导电区域的制造方法

    公开(公告)号：EP2015357A1

    公开(公告)日：2009-01-14

    申请号：EP07425423.6

    申请日：2007-07-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Benvenuti, Augusto ,  Cappelletti, Paolo ,  Bez, Roberto ,  Pirovano, Agostino

    IPC: H01L21/8229 ,  H01L27/102 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

    Abstract: A process for manufacturing an array of cells in a body (1) of semiconductor material wherein a common conduction region (11) of a first conductivity type and a plurality of shared control regions (12), of a second conductivity type, are formed in the body. The shared control regions (12) extend on the common conduction region (11) and are laterally delimited by insulating regions (32). Then, a grid-like layer (36) is formed on the body (1) to delimit a first plurality of empty regions (38) directly overlying the body and conductive regions of semiconductor material and the first conductivity type (44) are formed by filling the first plurality of empty regions (38), each conductive region forming, together with the common conduction region and an own shared control region (12), a bipolar junction transistor (20).

    Abstract translation: 于一体的制造单元的阵列的方法（1）的半导体材料的worin的第一导电类型的公共导电区（11）和一个第二导电类型的共享控制区域（12）的复数，在形成 身体。 共享控制区（12）上的公共导电区（11）延伸，并且尾盘反弹通过绝缘区域（32）分隔。 然后，网格状层（36）形成在所述主体（1）来分隔空区域的第一多个（38）直接覆盖所述主体和半导体材料的导电区域和第一导电类型（44）由形成 填充空区域（38），每个导电区域上形成的第一多个，与普通传导区在一起并且连接到自己的共享控制区域（12），双极结型晶体管（20）。

    Electronic device containing semiconductor polymers and corresponding manufacturing process
    7.
    发明公开
    Electronic device containing semiconductor polymers and corresponding manufacturing process 有权
    用半导体制造和相关聚合物的电子设备

    公开(公告)号：EP1814173A1

    公开(公告)日：2007-08-01

    申请号：EP06425040.0

    申请日：2006-01-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Sotgiu, Riccardo ,  Pirovano, Agostino

    IPC: H01L51/00 ,  H01L51/52

    CPC classification number: H01L51/5203 ,  Y10S428/917

    Abstract: Described herein is an electronic device (16) provided with an electrode (3, 4; 23, 34) and a region of polymeric material (15; 10) set in contact with the electrode. The electrode (3, 4; 23, 34) has a polysilicon region (3; 23) and a silicide region (4; 34), which coats the polysilicon region (3; 23) and is arranged, as interface, between the polysilicon region (3; 23) and the region of polymeric material (15; 10). The polysilicon region (3; 23) is doped with a doping level that is a function of a desired work function at the interface with the region of polymeric material (15; 10). The electronic device is, for example, a testing device for characterizing the properties of the polymeric material.

    Phase change memory cell with tubular heater and manufacturing method thereof
    8.
    发明公开
    Phase change memory cell with tubular heater and manufacturing method thereof 有权
    Phasenwechselspeicher mitrohrförmigerHeizstruktur sowie deren Herstellungsverfahren

    公开(公告)号：EP1710807A1

    公开(公告)日：2006-10-11

    申请号：EP05102811.6

    申请日：2005-04-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Varesi, Enrico ,  Pirovano, Agostino

    IPC: G11C16/02 ,  H01L45/00

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    Abstract: A phase change memory cell includes a phase change region of a phase change material, a heating element (30) of a resistive material, arranged in contact with the phase change region (33') and a memory element (35) formed in said phase change region at a contact area with the heating element (30). The contact area is in the form of a frame that has a width of sublithographic extent (S) and, preferably, a sublithographic maximum external dimension. The heating element (30) includes a hollow elongated portion which is arranged in contact with the phase change region (33').

    Abstract translation: 相变存储单元包括相变材料的相变区域，与相变区域（33'）接触地布置的电阻材料的加热元件（30）和形成在所述相位中的存储元件（35） 在与加热元件（30）的接触区域处的变化区域。 接触区域为具有亚光刻范围（S）的宽度的框架的形式，并且优选为亚光刻最大外部尺寸。 加热元件（30）包括与相变区域（33'）接触地布置的中空细长部分。

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