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    Device for reading nonvolatile memory cells, in particular analog flash memory cells
    11.
    发明公开
    Device for reading nonvolatile memory cells, in particular analog flash memory cells 有权
    An ere ere ere en en en en en en en en en en en en en en en en en en en en

    公开(公告)号：EP0997912A1

    公开(公告)日：2000-05-03

    申请号：EP98830626.2

    申请日：1998-10-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Canegallo, Roberto ,  Guaitini, Giovanni ,  Rolandi, Pier Luigi

    IPC: G11C27/00 ,  G11C16/06 ,  G11C11/56

    CPC classification number: G11C16/34 ,  G11C7/16 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26 ,  G11C27/005 ,  G11C2211/5642

    Abstract: The reading device (1) comprises an A/D converter (8) of n+m bits receiving an input signal (V1) correlated to the threshold voltage (VTH) of the memory cell (2), and supplying a binary output word (WT) of n+m bits. The A/D converter (8) is of a double conversion stage type (8), wherein a first A/D conversion stage (10) carries out a first analog/digital conversion of the input signal (V1), to supply at the output a first intermediate binary word (W1) of n bits, and the second A/D conversion stage (16) can be activated selectively to carry out a second analog/digital conversion of a difference signal (VD) correlated to the difference between the input signal (V1) and the value of the first intermediate binary word (W1). The second A/D conversion stage (16) generates at the output a second intermediate binary word (W2) of m bits supplied, with the first intermediate binary word (W1), to an adder (20) generating the binary output word (WT) of n+m bits.

    Abstract translation: 读取装置（1）包括接收与存储单元（2）的阈值电压（VTH）相关的输入信号（V1）的n + m位的A / D转换器（8），并且提供二进制输出字 WT）n + m位。 A / D转换器（8）是双转换级（8），其中第一A / D转换级（10）执行输入信号（V1）的第一模/数转换，以在 输出n位的第一中间二进制字（W1），并且可以选择性地激活第二A / D转换级（16），以对与第一中间二进制字（W1）之间的差相关的差信号（VD）进行第二模/数转换 输入信号（V1）和第一中间二进制字（W1）的值。 第二A / D转换级（16）在输出端产生与第一中间二进制字（W1）一起提供的m位的第二中间二进制字（W2）到生成二进制输出字（WT）的加法器（20） ）n + m位。

    Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMs
    12.
    发明公开
    Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMs 失效
    对于中并行编程的非易失性存储设备，特别是闪存EEPROM的和方法

    公开(公告)号：EP0913835A1

    公开(公告)日：1999-05-06

    申请号：EP97830550.6

    申请日：1997-10-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Canegallo, Roberto ,  Chioffi, Ernestina ,  Pasotti, Marco ,  Gerna, Danilo ,  Rolandi, Pier Luigi

    IPC: G11C16/06

    CPC classification number: G11C16/3459 ,  G11C16/3454

    Abstract: The programming method comprises the steps of applying a programming pulse to a first cell (2) and simultaneously verifying the present threshold value of at least a second cell (2); then verifying the present threshold value of the first cell and simultaneously applying a programming pulse to the second cell. In practice, during the entire programming operation, the gate terminal of both the cells is biased to a same predetermined gate voltage (V PCX ) and the source terminal is connected to ground; the step of applying a programming pulse is carried out by biasing the drain terminal of the cell to a predetermined programming voltage (V P ) and the step OF verifying is carried out by biasing the drain terminal of the cell to a read voltage (V R ) different from the programming voltage. Thereby, switching between the step of applying a programming pulse and verifying is obtained simply by switching the drain voltage of the cells.

    Abstract translation: 该编程方法包括施加编程脉冲到第一小区（2），并同时验证至少一个第二小区（2）的本阈值的工序; 然后验证所述第一小区的当前阈值，并且同时施加编程脉冲到所述第二小区。 在实践中，整个编程操作期间，这两个单元的栅极端子被偏置到一个相同的栅极预定电压（VPCX）和源极端子连接到地; 施加编程脉冲的步骤是通过偏置单元的漏极端子至预定编程电压（VP）和检验步骤是通过偏置单元的漏极端子的读出电压（VR）不同开展开展 从编程电压。 由此，施加编程脉冲的步骤和验证之间的切换通过切换单元的漏极电压简单地获得。

    Communication system between first and second independently clocked devices
    13.
    发明公开
    Communication system between first and second independently clocked devices 有权
    一个第一和一个第二独立计数设备之间的通信系统

    公开(公告)号：EP2075710A2

    公开(公告)日：2009-07-01

    申请号：EP08022447.0

    申请日：2008-12-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

    IPC: G06F13/42

    CPC classification number: H04L7/10 ,  H04L7/0037

    Abstract: The invention relates to a communication system between a first and a second independently clocked devices (L,R), in particular chips, comprising, for each device, at least a transmitter (TXL,TXR) and a receiver (RXL,RXR) connected to each other in a crossed way in correspondence of an inter-chip communication channel (ICC). Advantageously according to the invention, the communication system further comprises a synchronizer (40) in turn including at least a first and a second synchronization block (20L,20R), having respective input terminals (INrL,INrR) connected to the receivers (RXL,RXR) and respective output terminals (OUTtL,OUTtR) connected to the transmitters (TXL,TXR) and comprising at least:
    - a test pattern generator (23);
    - comparison means (21,22) to check a matching between stored and received test pattern signals; and
    - a delay block (26) able to change the clock phases.

    Abstract translation: 本发明涉及到一个第一和一个第二unabhängig时钟控制装置（L，R）之间的通信系统，特别是芯片，其包括，对于每一个设备，至少一个发送器（TXL，TXR）和接收器（RXL，RXR）连接 海誓山盟在一个芯片间通信信道（ICC）的对应关系的交叉方法。 有利的是雅丁到本发明，该通信系统还包括又一个同步器（40）包括至少一个第一和一个第二同步块（20L，20R），其具有连接到所述接收器respectivement输入端子（INrL，INRR）（RXL， RXR）和相应的输出端子连接到所述发射机（TXL，TXR）和包含至少（OUTtL，OUTtR）： - 测试图案生成器（23）; - 比较装置（21,22），以检查存储和接收的测试模式信号之间的匹配; 和 - 一个延迟块（26），其能够改变时钟相位。

    Asynchronous interconnection system for 3D inter-chip communication
    14.
    发明公开
    Asynchronous interconnection system for 3D inter-chip communication 有权
    不同步的Verbindungssystemfür3D-Inter-Chip-Kommunikation

    公开(公告)号：EP1940028A1

    公开(公告)日：2008-07-02

    申请号：EP06027047.7

    申请日：2006-12-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fazzi, Alberto ,  Guerrieri, Roberto ,  Magagni, Luca ,  Ciccarelli, Luca ,  Canegallo, Roberto

    IPC: H03K19/0185 ,  H03K19/00

    CPC classification number: H03K19/018521 ,  H03K3/356165

    Abstract: The present invention relates to a asynchronous interconnection system (10) comprising a transmitter circuit (11) and a receiver circuit (12) inserted between inserted between respective first and second voltage references (Vcctx, GNDtx - Vccrx, GNDrx) and having respective transmitter and receiver nodes (TX, RX) coupled in a capacitive manner.
    Advantageously according to the invention, the receiver circuit (12) comprises:
    - a recovery stage (13) inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) and connected to the receiver node (RX); and
    - a state control stage (14), in turn inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) connected to the recovery stage (13) correspondence with a first feedback node (X) providing a first control signal (Recovery Enable) and having a second feedback node (Z*) connected in a feedback manner to the recovery stage (13).
    The recovery stage (13) comprises a first feedback loop (Loop 1) connected to the first feedback node (X) and acting in such a way to recover a received voltage signal and a feedback loop (Loop2) connected to the second feedback node (Z*) of the state control stage (14) and acting in such a way to deactivate the recovery feedback on the receiver node (RX) and guarantee that the receiver node (RX) is let in a high impedance state.

    Abstract translation: 本发明涉及一种异步互连系统（10），包括发射机电路（11）和插入在相应的第一和第二电压基准（Vcctx，GNDtx-Vccrx，GNDrx）之间的接收机电路（12），并且具有各自的发射机和 接收器节点（TX，RX）以电容方式耦合。 有利地，根据本发明，接收器电路（12）包括： - 插入在接收器电路（12）的第一和第二电压基准（Vccrx，GNDrx）之间并连接到接收器节点（RX）的恢复级（13） ; 以及 - 状态控制级（14），其又插入在与恢复级（13）连接的接收器电路（12）的第一和第二电压基准（Vccrx，GNDrx）之间，与第一反馈节点（X）对应，提供 第一控制信号（恢复使能）并且具有以反馈方式连接到恢复级（13）的第二反馈节点（Z *）。 恢复阶段（13）包括连接到第一反馈节点（X）的第一反馈回路（回路1），并以这样一种方式起作用以恢复接收的电压信号和连接到第二反馈节点的反馈回路（Loop2） 状态控制级（14）的Z *），并以这样一种方式使接收器节点（RX）上的恢复反馈失效，并保证接收器节点（RX）处于高阻抗状态。

    Charge pump booster device with transfer and recovery of the charge
    18.
    发明公开
    Charge pump booster device with transfer and recovery of the charge 有权
    电荷泵电路和升压装置与电荷转移和恢复

    公开(公告)号：EP1158654A1

    公开(公告)日：2001-11-28

    申请号：EP00830105.3

    申请日：2000-02-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Zanuccoli, Mauro, c/o Deis Universita' Bologna ,  Canegallo, Roberto ,  Dozza, Davide, c/o Deis Universita' Bologna

    IPC: H02M3/07

    CPC classification number: H02M3/073 ,  H02M2003/075

    Abstract: The load pump booster device (1) with transfer and recovery of the charge comprises a charge pump circuit (2) with an output terminal (30.N) which is connected to a load capacitor (12) by means of a load node (50). In turn, the charge pump circuit (2) comprises a plurality of transfer transistors (15.0, ..., 15.j, ..., 15.N) which are connected to one another in series, and define a plurality of transfer nodes (30.0, ..., 30.j, ..., 30.N). Each transfer node (30.0, ..., 30.j, ..., 30.N) is connected to a storage capacitor (14.0, ..., 14.j, ..., 14.N). The booster device (1) also comprises a plurality of controlled switches (40.0, ..., 40.j, ..., 40.N) which are interposed between the said load node (50) and a respective transfer node (30.0, ..., 30.j, ..., 30.N), in order to connect to the said load node (50) a single one of the said transfer nodes (30.0, ..., 30.j, ..., 30.N). By this means, between the load capacitor (12) and the storage capacitors (14.0, ..., 14.j, ..., 14.N) there takes place a phase of transfer of charge followed by a phase of recovery of charge, from the storage capacitors (14.0, ..., 14.j, ..., 14.N) to the load capacitor (12).

    Method for multilevel programming of a nonvolatile memory, and a multilevel nonvolatile memory
    20.
    发明公开
    Method for multilevel programming of a nonvolatile memory, and a multilevel nonvolatile memory 失效
    韦尔法赫伦

    公开(公告)号：EP0913832A1

    公开(公告)日：1999-05-06

    申请号：EP97830566.2

    申请日：1997-11-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Rolandi, Pier Luigi ,  Canegallo, Roberto ,  Gerna, Danilo ,  Chioffi, Ernestina

    IPC: G11C11/56 ,  G11C27/00

    CPC classification number: G11C11/5621 ,  G11C11/5628

    Abstract: The programming method comprises the steps of: a) determining (140) a current value (V eff ) of the threshold voltage (V th ); b) acquiring (100) a target value (V p ) of the threshold voltage; c) calculating (150) a first number of gate voltage pulses necessary to take the threshold voltage from the current value to the target value; d) applying (160) a second number (N2) of consecutive voltage pulses to the gate terminal of the cell, said second number being correlated to the first number and having a uniformly increasing amplitude; e) then measuring (170) a current value (V eff ) of the threshold voltage; and repeating steps c) to e) until a final threshold value is obtained.

    Abstract translation: 编程方法包括以下步骤：a）确定（140）阈值电压（Vth）的当前值（Veff）; b）获取（100）阈值电压的目标值（Vp）; c）计算（150）将阈值电压从当前值到目标值所需的第一数量的栅极电压脉冲; d）将连续电压脉冲的第二数量（N 2）施加到所述单元的所述栅极端子，所述第二数量与所述第一数量相关并具有均匀增加的幅度; e）然后测量（170）阈值电压的电流值（Veff）; 并重复步骤c）至e），直到获得最终阈值。

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