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    Process for manufacturing electronic memory devices with cells matrix having virtual ground
    13.
    发明公开
    Process for manufacturing electronic memory devices with cells matrix having virtual ground 有权
    用于电子存储器装置具有单元阵列虚拟地制造工艺

    公开(公告)号：EP1032035A1

    公开(公告)日：2000-08-30

    申请号：EP99830100.6

    申请日：1999-02-26

    Applicant: STMicroelectronics S.r.l. ,  Wafer Scale Integration, Inc.

    Inventor： Pozzoni, Pierantonio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Irani, Ruston

    IPC: H01L21/8247

    CPC classification number: H01L27/11521

    Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and comprising at least a matrix of floating gate memory cells (1), the matrix being formed on a semiconductor substrate (2) with a plurality of continuous bit lines (10) extending across the substrate (2) as discrete parallel strips, comprising at least the following steps:

    forming an oxide layer (3) over the matrix region;
    depositing the semiconductor throughout with a stack structure which comprises a first conductor layer (4), first dielectric layer (5), and second conductor layer (6);
    forming a second dielectric layer (7);
    defining floating gate regions (13) by photolithography using a mask of "POLY1 along a first predetermined direction", and associated etching, to define, in said stack structure, a plurality of parallel openings (9);
    implanting said parallel openings (9) to confer a predetermined conductivity on the bit line (10) regions;
    filling the parallel openings (12) with a photo-sensitive material (11) to protect the matrix bit lines (10).

    Abstract translation: 一种用于制造具有虚地电子半导体集成电子存储器设备和包括至少浮动栅极存储器单元的一个矩阵处理（1）中，基体被连续位线的延伸的多个（10）形成在半导体衬底（2） 横跨基片（2）作为离散的平行条带，其包括至少以下步骤：在所述矩阵区域氧化物层（3）上; 沉积半导体整个具有堆叠结构，其包括第一导体层（4），第一电介质层（5）和第二导体层（6）; 形成第二电介质层（7）; 使用的“沿第一预定方向POLY1”掩模，和相关联的蚀刻， - 定义浮置栅极区域（13），通过光刻，以限定在所述堆叠结构，平行的开口（9）的多元性; 注入所述平行的开口（9），以赋予对位线（10）的区域的预定导电性; 填充开口（12）在平行（11）光敏材料，以保护基质的位线（10）。

    Method for forming a plurality of parallel floating gate regions by avoiding poly stringers formation
    17.
    发明公开
    Method for forming a plurality of parallel floating gate regions by avoiding poly stringers formation 失效
    制造多个平行的浮栅区域的免费同时避免多晶硅残基的形成的方法

    公开(公告)号：EP0902463A1

    公开(公告)日：1999-03-17

    申请号：EP97830433.5

    申请日：1997-08-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Cassio, Valerio ,  Wurthwein, Arturo

    IPC: H01L21/321 ,  H01L21/8247

    CPC classification number: H01L27/11521 ,  H01L21/32139

    Abstract: A method of manufacturing a plurality of floating gate regions lying parallel on a semiconductor substrate (10), and of inhibiting the formation of residue materiallaterally contiguous to each floating gate region, comprises the following steps: growing a thin oxide layer (13) over the semiconductor substrate (10); depositing a first layer (14) of polysilicon to fully cover the first thin oxide layer; growing and/or depositing an intermediate dielectric layer (15) over the first layer (14) of polysilicon; depositing a second layer (16) of polysilicon to fully cover the intermediate dielectric layer (15). This method further comprises the steps of depositing a final dielectric layer (17) to cover the previously deposited and/or grown layers (13,14,15,16); depositing a layer of resist onto the final dielectric layer, followed by a photolithographing step to define a planar geometry bounding the floating gate regions; and carrying out a first etching to only transfer this planar geometry onto the final dielectric layer (17), thereby producing a mask for a late second etching of the self-aligned type; thoroughly removing the layer of resist; carrying out a second self-aligned etching to spatially define the floating gate regions with a vertical profile.

    Abstract translation: 制造浮在一个半导体衬底（10）位于平行的栅极区域中的多个方法，和残余材料尾盘反弹邻接的各浮栅区的形成，抑制的方法包括以下步骤：生长在一薄的氧化物层（13） 半导体衬底（10）; 沉积多晶硅完全覆盖第一薄氧化物层的第一层（14）; 生长和/或在多晶硅的第一层（14）中间介电层（15）上沉积; 沉积多晶硅的第二层（16）完全覆盖中间介电层（15）。 该方法还包括沉积最终介电层（17），以覆盖先前沉积和/或生长的层（13,14,15,16）的步骤; 沉积抗蚀剂层到最终的介电层，接着是步骤photolithographing以限定平面的几何形状界定浮栅区; 并进行第一蚀刻，以仅传输该平面的几何形状到最终的介电层（17），由此产生的自对准型的后期第二蚀刻的掩模; 彻底除去抗蚀剂的层; 进行第二自对准蚀刻到空间上与垂直轮廓限定在浮置栅极区域。

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