公开(公告)号：EP2261969A1

公开(公告)日：2010-12-15

申请号：EP10185628.4

申请日：2005-04-18

Applicant: STMicroelectronics S.r.l.

Inventor： Ponza, Anna ,  Depetro, Riccardo ,  Montanini, Pietro

IPC: H01L21/78

CPC classification number: H01L21/78

Abstract: A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer (5') partially suspended above a semiconductor substrate (2) and constrained to the substrate (2) by temporary anchorages (10, 15'); dividing the layer (5') into a plurality of portions (13) laterally separated from one another; and removing the temporary anchorages (10, 15'; 38), in order to free the portions (13).

Abstract translation: 用于制造半导体芯片中的集成器件的工艺设想：形成半导体衬底（2）部分悬置并通过临时锚固（10,15'）约束到衬底（2）的半导体层（5'）; 将层（5'）分成彼此横向分离的多个部分（13）; 以及移除所述临时锚固件（10,15'; 38），以便释放所述部分（13）。

公开(公告)号：EP1195815B1

公开(公告)日：2007-07-18

申请号：EP00830658.1

申请日：2000-10-06

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo

IPC: H01L27/08

CPC classification number: H01L28/10 ,  H01L27/08

公开(公告)号：EP0889591B1

公开(公告)日：2004-03-03

申请号：EP97830327.9

申请日：1997-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Scian, Enrico ,  Martignoni, Fabrizio ,  Depetro, Riccardo

IPC: H03K17/10 ,  H03K19/003 ,  G05F3/20 ,  H01L27/02

CPC classification number: H03K19/00315 ,  G05F3/205 ,  H01L27/0251

公开(公告)号：EP1296380A1

公开(公告)日：2003-03-26

申请号：EP01830595.3

申请日：2001-09-20

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Manzini, Stefano

IPC: H01L29/94

CPC classification number: H01L29/417 ,  H01L29/94

Abstract: High-Q, variable capacitance capacitor (20, 20'), comprising a pocket (22) of semiconductor material; a field insulating layer (23), covering the pocket; an opening (24) in the field insulating layer, delimiting a first active area (24); an access region (25) formed in the active area and extending at a distance from a first edge (24a) of the active area and adjacent to a second edge (24b) of the active area. A portion (26) of the pocket (22) is comprised between the access region (15) and the first edge (24a) and forms a first armature; an insulating region (30) extends above the portion (26) of said body, and a polysilicon region (31) extends above the insulating region (30) and forms a second armature. A portion of the polysilicon region extends above the field insulating layer (23), parallel to the access region (25); a plurality of contacts (32) are formed at a mutual distance along the portion of the polysilicon region (31) extending above the field insulating layer (23).

Abstract translation: 高Q型可变容性电容器（20,20'），包括半导体材料的凹穴（22）; 覆盖所述口袋的场绝缘层（23）; 在所述场绝缘层中的开口（24），限定第一有效区域（24）; 形成在有源区域中并且与有源区域的第一边缘（24a）一定距离并且与有源区域的第二边缘（24b）相邻延伸的访问区域（25）。 袋（22）的一部分（26）包括在接近区（15）和第一边（24a）之间并形成第一电枢; 绝缘区域（30）在所述主体的部分（26）上方延伸，并且多晶硅区域（31）在绝缘区域（30）上延伸并形成第二电枢。 多晶硅区域的一部分平行于接入区域（25）延伸到场绝缘层（23）的上方。 多个触点（32）沿着在场绝缘层（23）上方延伸的多晶硅区域（31）的部分相互间隔地形成。

公开(公告)号：EP1291924A1

公开(公告)日：2003-03-12

申请号：EP01830574.8

申请日：2001-09-10

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Ponza, Anna ,  Gallerano, Antonio

IPC: H01L29/78 ,  H01L29/41 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238

Abstract: An MOS electronic device (30) including: a drain region (31); a field insulating layer (33), covering the drain region; an opening (38) in the field insulating layer delimiting an active area (34); a body region (40) housed in the active area; a source region (41) housed in the body region. A portion of the body region comprised between the drain region and the source region forms a channel region (43). A polycrystalline silicon structure (45) extends along the edge of the opening delimiting the active area, partially on top of the field insulating layer and partially on top of the active layer. The polycrystalline silicon structure (45) comprises a gate region (46) extending along a first portion of the edge on top of the channel region (43) and partially surrounding the source region (41) and a non-operative region (47) extending along a second portion of the edge, electrically insulated and at a distance from the gate region, so as to reduce the drain/gate capacity and to increase the cutoff frequency of the MOS device.

Abstract translation: 一种MOS电子器件（30），包括：漏极区域（31）; 场绝缘层（33），覆盖所述漏区; 限定有源区域（34）的场绝缘层中的开口（38）; 容纳在所述活动区域中的身体区域（40） 容纳在身体区域中的源区域（41）。 包括在漏极区域和源极区域之间的体区的一部分形成沟道区域（43）。 多晶硅结构（45）沿着限定有源区的开口的边缘延伸，部分地在场绝缘层的顶部上并部分地在有源层的顶部上延伸。 多晶硅结构（45）包括沿沟道区域（43）的顶部上的边缘的第一部分延伸并且部分地围绕源极区域（41）的一个栅极区域（46）和一个非操作区域（47） 沿着边缘的第二部分电绝缘并且离开栅极区一定距离，以便降低漏极/栅极容量并增加MOS器件的截止频率。

公开(公告)号：EP2264753A2

公开(公告)日：2010-12-22

申请号：EP10183038.8

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/74 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (500). The method includes the steps of providing an SOI substrate (505) including a semiconductor substrate (510), an insulating layer (515) on the semiconductor substrate, and a semiconductor starting layer (512) on the insulating layer, the substrate and the starting layer being of a first type of conductivity, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (542) of the first type of conductivity embedding the starting layer on the insulating layer, forming at least one insulating trench (558) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (560) and at least one further insulated region (561), and integrating components (580) of the device in the insulated regions, the components being insulated from the substrate by the insulating layer; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (520) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, each contact trench clearing a corresponding portion (530b,530s) of the starting layer, of the insulating layer and of the substrate, implanting dopants of a second type of conductivity different from the first type into at least part of the cleared portions, wherein the epitaxial growing is further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material, the dopants diffusing during the epitaxial growing to form an insulating region (545) of the second type of conductivity enclosing the at least one contact trench of each further insulated region, and integrating further components (580) of the device in each further insulated region, the further components being insulated from the substrate by a junction formed by the corresponding insulating region with the active layer and/or the substrate when reverse-biased.

Abstract translation: 提出了一种用于制造集成电子设备（500）的方法。 该方法包括以下步骤：提供包括半导体衬底（510），在半导体衬底上的绝缘层（515）以及在绝缘层上的半导体起始层（512）的SOI衬底（505），衬底和起始 所述外延生长工艺被施加到所述起始层以获得在所述绝缘层上嵌入所述起始层的第一类型的导电性的更厚的半导体活性层（542） 形成从有源层的暴露表面延伸到绝缘层的至少一个绝缘沟槽（558），所述至少一个绝缘沟槽将有源层分隔成绝缘区域（560）和至少一个另外的绝缘区域（561）， 以及将所述器件的部件（580）集成在所述绝缘区域中，所述部件通过所述绝缘层与所述衬底绝缘; 在根据本发明实施例的解决方案中，所述方法还包括：在执行外延生长工艺的步骤之前，形成至少一个接触沟槽（520），所述接触沟槽从起始层的暴露表面延伸到衬底， 每个另外的绝缘区域，每个接触沟槽清除起始层，绝缘层和衬底的对应部分（530b，530s）;将不同于第一类型的第二类型导电性的掺杂物注入至少部分 其中外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充每个接触沟槽，掺杂剂在外延生长期间扩散以形成第二类型导电性的绝缘区域（545） 每个另外的绝缘区域的至少一个接触沟槽，并且还将每个进一步的器件的组件（580）集成在一起 所述另外的部件在反向偏置时通过由所述对应的绝缘区域与所述有源层和/或所述衬底形成的结与所述衬底绝缘。

公开(公告)号：EP1577952A1

公开(公告)日：2005-09-21

申请号：EP04100960.6

申请日：2004-03-09

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Manzini, Stefano

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7816

Abstract: An insulated gate field-effect transistor (100;300) is proposed, including a body region (115) of a first conductivity type formed in a semiconductor material layer (105) in correspondence of the front surface, a gate electrode (112) disposed over the body region with interposition of a gate dielectric (110), and a source region (120,145;320,145) and a drain region (125,150) of second conductivity type opposite to the first conductivity type, respectively formed in the body region and the semiconductor material layer. The source and drain region are provided spaced apart from each other by a channel zone (130) in a portion of the body region underlying the gate electrode, and a drift portion (135) of the semiconductor material layer between the channel zone and the drain region, the insulated gate extending over the drift portion. The drain region is located at a depth compared to a top surface of the semiconductor material layer to move charge carriers in the drift portion away from an interface between the semiconductor material layer and the gate dielectric.

Abstract translation: 一种绝缘栅晶体管，包括具有前表面的半导体材料层，主体区域，设置在主体区域上的绝缘栅极，插入栅极电介质，以及源极和漏极区域，源区域形成在体区中 和形成在半导体材料层中的漏极区。 源极和漏极区域通过绝缘栅极下方的主体区域的一部分中的沟道区彼此间隔开，并且半导体材料层的电荷载流子漂移部分在沟道区域和漏极区域之间，绝缘栅极 在电荷载流子漂移部分上延伸。 漏极区域位于与前表面相比的深度处，以使电荷载流子在电荷载流子漂移部分中远离半导体材料层和栅极电介质之间的界面移动。

公开(公告)号：EP0757389B1

公开(公告)日：2001-09-26

申请号：EP95830346.3

申请日：1995-07-31

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Novelli, Aldo

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L29/7824 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/7393 ,  H01L29/7801 ,  H01L29/7817

公开(公告)号：EP0913925A1

公开(公告)日：1999-05-06

申请号：EP97830559.7

申请日：1997-10-31

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Martignoni, Fabrizio ,  Scian, Enrico

IPC: H03F1/00 ,  H03K19/0185

CPC classification number: H03K19/018585

Abstract: The invention relates to a high-voltage final output stage (1) for driving an electric load, of the type which comprises a complementary pair (3) of transistors connected between first (Vdd) and second (Vss) supply voltage references, and at least one PMOS pull-up transistor (MP1) connected in series with an NMOS pull-down transistor (MN). The stage (1) comprises an additional PMOS transistor (MP2) connected in parallel with the pull-up transistor (MP1) and having the body terminal in common therewith. More particularly, the body terminals of both PMOS transistors (MP1,MP2) are formed in the semiconductor within a common well which can withstand high voltages, and the additional transistor (MP2) is a thick oxide PMOS power transistor.

Abstract translation: 本发明涉及用于驱动电负载的高压最终输出级（1），其包括连接在第一（Vdd）和第二（Vss）电源电压基准之间的晶体管的互补对（3），并且在 与NMOS下拉晶体管（MN）串联连接的至少一个PMOS上拉晶体管（MP1）。 级（1）包括与上拉晶体管（MP1）并联连接并且与其主体端子共同连接的附加PMOS晶体管（MP2）。 更具体地说，两个PMOS晶体管（MP1，MP2）的主体端子形成在可承受高电压的公共阱内的半导体中，附加晶体管（MP2）是厚氧化物PMOS功率晶体管。

公开(公告)号：EP0714135B1

公开(公告)日：1999-01-13

申请号：EP94830530.5

申请日：1994-11-08

Applicant: STMicroelectronics S.r.l.

Inventor： Contiero, Claudio ,  Depetro, Riccardo

IPC: H01L29/41 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/4238