公开(公告)号：EP1182637A1

公开(公告)日：2002-02-27

申请号：EP00830587.2

申请日：2000-08-22

Applicant: STMicroelectronics S.r.l. ,  TECDIS S.p.A.

Inventor： Gariboldi, Roberto ,  Lavorerio, Riccardo ,  Sala, Leonardo ,  Nidasio, Giovanni

IPC: G09G3/36 ,  G09G5/36

CPC classification number: G09G5/395 ,  G09G3/3611 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/0278 ,  G09G2360/02 ,  G09G2360/12

Abstract: Presented is a new memory controller for use in a display, such as a liquid crystal display of the type comprising a set of first drivers (24), and a set of second drivers (26), a portion of which can be converted to said first drivers (26b). Also included is a RAM memory (62) structured to accept data at an input and output said data to the sets of first (24) and second (26) drivers when a master clock signal is received at said RAM memory (62). The memory controller includes a clock signal generator structured to generate said master clock signal; and a control signal generator circuit structured to generate control signals for said RAM memory (62) and said sets of first (24) and second (26) drivers. An important advantage to this memory controller is that it includes a set of auxiliary registers (52) structured to temporarily store a first portion of said data received from said RAM memory (62) after receiving a slave clock cycle, and said set of auxiliary registers (52) structured to output said first portion of data into said portion of said second drivers converted to said first drivers (26b) after receiving said master clock signal. A method is also disclosed that uses the above structure in order to perform the steps of using a folded memory as a way to increase the utilization rate of memory within the display controller.

Abstract translation: 提出了一种用于显示器的新的存储器控​​制器，例如包括一组第一驱动器（24）的类型的液晶显示器和一组第二驱动器（26），其一部分可以转换为所述 第一个司机（26b）。 还包括RAM存储器（62），其被构造为当在所述RAM存储器（62）处接收到主时钟信号时，在输入端接收数据并将所述数据输出到第一（24）和第二（26）驱动器的组。 存储器控制器包括被构造为产生所述主时钟信号的时钟信号发生器; 以及控制信号发生器电路，其被构造为产生用于所述RAM存储器（62）和所述第一（24）和第二（26）驱动器组的控制信号。 该存储器控制器的一个重要优点是它包括一组辅助寄存器（52），其被构造为在接收到从时钟周期之后临时存储从所述RAM存储器（62）接收到的所述数据的第一部分，并且所述一组辅助寄存器 （52），其被构造为在接收到所述主时钟信号之后将所述第一数据部分输出到所述转换成所述第一驱动器（26b）的所述第二驱动器的所述部分。 还公开了一种使用上述结构以便执行使用折叠存储器作为增加显示控制器内的存储器的利用率的方式的方法。

公开(公告)号：EP1104106A2

公开(公告)日：2001-05-30

申请号：EP00204130.9

申请日：2000-11-21

Applicant: STMicroelectronics S.r.l.

Inventor： Novelli, Aldo ,  Gariboldi, Roberto ,  Genova, Angelo ,  Filippo, Roberto

IPC: H03K17/06

CPC classification number: H03K17/04123 ,  H03K17/063

Abstract: A high side circuit is described which comprises at least one power device (1) having a first non drivable terminal (D) connected to a supply voltage (Vcc), at least one load (2) connected between a second non drivable terminal (S) of the power device (1) and ground, and driving circuitry (10). The driving circuitry (10) comprises suitable dimensioned transistors (M1, M2, M3) which are connected to each other and to a higher voltage (Vboot) than the supply voltage (Vcc) in order to control the turning on and the turning off of the power device (1) and to minimize the potential difference between the second non drivable terminal (S) and a drivable terminal (G) of the power device (1) during the turning off state to avoid the re-turning on of the same power device.

Abstract translation: 描述了一种高侧电路，其包括至少一个功率器件（1），其具有连接到电源电压（Vcc）的第一非驱动端子（D），连接在第二不可驱动端子（S）之间的至少一个负载（2） ）和驱动电路（10）。 驱动电路（10）包括彼此连接并具有比电源电压（Vcc）更高的电压（Vboot）的合适的尺寸尺寸的晶体管（M1，M2，M3），以便控制导通和断开 功率器件（1），并且在关闭状态期间将功率器件（1）的第二不可驱动端子（S）和可驱动端子（G）之间的电位差最小化以避免重新接通 电源设备。

公开(公告)号：EP0896268A1

公开(公告)日：1999-02-10

申请号：EP97830415.2

申请日：1997-08-07

Applicant: STMicroelectronics S.r.l.

Inventor： Genova, Angelo ,  Cantone, Giuseppe ,  Gariboldi, Roberto

IPC: G05F1/00 ,  G05F1/575 ,  H03K17/16

CPC classification number: H03K17/162 ,  G05F3/262

Abstract: An integrated device (105) for a switching system (100) comprises control means (110) for generating at least one switching control signal (Sh), reference means (120) for generating at least one reference quantity (Qref), means (110) for using the reference quantity (Qref), means (130) for storing the reference quantity (Qref), switch means (122) which, in a first operative condition, connect the reference means (120) to the using means (110) and to the storage means (130) in order to apply the reference quantity (Qref) thereto and, in a second operative condition, disconnect the reference means (120) from the using means (110) and connect the storage means (130) to the using means (110) in order to apply the stored reference quantity thereto, and filtering means (135) for keeping the switch means (122) in the second operative condition for a filtering period (Tf) in accordance with the switching of the control signal (Sh).

Abstract translation: 一种用于切换系统（100）的集成设备（105）包括用于产生至少一个切换控制信号（Sh）的控制装置（110），用于产生至少一个参考数量（Qref）的参考装置（120） ），用于存储参考数量（Qref）的装置（130），用于存储参考数量（Qref）的装置（130），在第一操作状态下将参考装置（120）连接到使用装置（110）的开关装置 并且向存储装置（130）提供参考数量（Qref），并且在第二操作条件下，使用参考装置（120）与使用装置（110）断开连接，并将存储装置（130）连接到 使用装置（110），以便将存储的参考数据应用于其中;以及滤波装置（135），用于根据控制的切换将开关装置（122）保持在第二操作状态中的过滤周期（Tf） 信号（Sh）。

公开(公告)号：EP1184962B1

公开(公告)日：2006-05-17

申请号：EP00830586.4

申请日：2000-08-22

Applicant: STMicroelectronics S.r.l. ,  TECDIS S.p.A.

Inventor： Gariboldi, Roberto ,  Lavorerio, Riccardo ,  Sala, Leonardo ,  Nidasio, Giovanni

IPC: H02M3/07 ,  G05F1/563

CPC classification number: H02M3/073

公开(公告)号：EP1583070A1

公开(公告)日：2005-10-05

申请号：EP04425227.8

申请日：2004-03-30

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Sala, Leonardo ,  Bagarelli, Fulvio ,  Gariboldi, Roberto

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3696 ,  G09G3/2011 ,  G09G3/3648 ,  G09G2310/027 ,  G09G2320/0219 ,  G09G2320/0276 ,  G09G2320/0673

Abstract: Described is a method for designing a structure for driving display devices.
In one embodiment the method for designing a structure for driving display devices comprises the steps of: considering the transmittance characteristics in relation to the voltage applied to a plurality of liquid crystal displays; defining a transmittance curve on the basis of the voltage applied to said liquid crystals, for each liquid crystal display of said plurality; applying a gamma correction, with different values of the gamma exponent, to each previously defined curve; applying a kickback correction to each previously defined curve; positioning a plurality of branch points along said curves; determining a resisitance value for each branch point and for each of said one curve for each display; choosing the value of minimum resistance for each branch point; choosing the value of maximum resistance per each branch point; calculating the difference between said value of minimum resistance for each branch point and said value of maximum resistance for each branch point; defining for each branch point a value of fixed resistance equal to said value of minimum resistance; defining for each branch point an interval of values for a variable resistance equal to said difference.

Abstract translation: 的方法创建的显示装置driverby步骤，包括：考虑到在关系的透射率特性的电压施加到多个液晶显示装置; 基于施加到所述显示器，每个显示器的电压的限定透射率曲线; 施加伽马校正，与伽马指数的不同的值，每个透射率曲线; 施加反冲校正每条曲线; 沿着所述曲线定位分支点; 确定性采矿每个分支点和用于为每个显示每条曲线的电阻值; 选择用于每个分支点的最小电阻值; 选择的每个分支点处的最大电阻值; 计算所述最低电阻值和每个分支点所述最大电阻值之间的差; - 定义为每个分支点处的固定电阻值等于所述最小电阻值; - 定义为值的间隔为等于所述差的可变电阻的每个分支点。

公开(公告)号：EP1104106A3

公开(公告)日：2004-01-14

申请号：EP00204130.9

申请日：2000-11-21

Applicant: STMicroelectronics S.r.l.

Inventor： Novelli, Aldo ,  Gariboldi, Roberto ,  Genova, Angelo ,  Filippo, Roberto

IPC: H03K17/06

CPC classification number: H03K17/04123 ,  H03K17/063

Abstract: A high side circuit is described which comprises at least one power device (1) having a first non drivable terminal (D) connected to a supply voltage (Vcc), at least one load (2) connected between a second non drivable terminal (S) of the power device (1) and ground, and driving circuitry (10). The driving circuitry (10) comprises suitable dimensioned transistors (M1, M2, M3) which are connected to each other and to a higher voltage (Vboot) than the supply voltage (Vcc) in order to control the turning on and the turning off of the power device (1) and to minimize the potential difference between the second non drivable terminal (S) and a drivable terminal (G) of the power device (1) during the turning off state to avoid the re-turning on of the same power device.

公开(公告)号：EP1365384A1

公开(公告)日：2003-11-26

申请号：EP02425326.2

申请日：2002-05-23

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Sala, Leonardo ,  Domanin, Daniele ,  Gariboldi, Roberto

IPC: G09G3/36

CPC classification number: G09G3/3625 ,  G09G3/2018 ,  G09G3/2022 ,  G09G2320/0247 ,  G09G2320/0266

Abstract: The present invention relates to a driving method for flat panel display devices, particularly a driving method combining a Multi Line Addressing (MLA) technique and a Frame Rate Control (FRC) technique, for flat panel display devices such as Liquid Crystal Display (LCD).
In an embodiment the method of driving an image display device comprises the following steps: dividing row electrodes of an image device, having a plurality of row electrodes and a plurality of column electrodes, into a plurality of subgroups; selecting one of the plurality of said subgroups having a prefixed number of electrodes; performing a grey scale display by a frame rate control (FRC) by using a prefixed number of frames and a prefixed number of bits representing the grey levels; decomposing one of said frame in a number of time instants proportional to said prefixed number of electrodes; putting the bits representing the grey levels equally distributed in said prefixed number of frames.

Abstract translation: 本发明涉及用于平板显示装置的驱动方法，特别是组合多行寻址（MLA）技术和帧速率控制（FRC）技术的驱动方法，用于诸如液晶显示器（LCD）的平板显示装置， 。 在一个实施例中，驱动图像显示装置的方法包括以下步骤：将具有多个行电极和多个列电极的图像装置的行电极分成多个子组; 选择所述多个所述子组中的一个具有预定数量的电极; 通过使用预定数量的帧和表示灰度级的前缀位数来执行帧速率控制（FRC）的灰度级显示; 在与所述预定数量的电极成比例的多个时刻中分解所述帧中的一个; 将表示灰度级的位平均分配在所述前缀数目的帧中。

公开(公告)号：EP0782235B1

公开(公告)日：2001-11-14

申请号：EP95830550.0

申请日：1995-12-29

Applicant: STMicroelectronics S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Pulvirenti, Francesco ,  Bontempo, Gregorio ,  Gariboldi, Roberto

IPC: H02H1/00 ,  H03K17/082

CPC classification number: H03K17/0822 ,  H03K2017/0806 ,  H03K2217/0063 ,  H03K2217/0072

公开(公告)号：EP0743529B1

公开(公告)日：2004-07-28

申请号：EP95830204.4

申请日：1995-05-16

Applicant: STMicroelectronics S.r.l. ,  CO.RI.M.ME.

Inventor： Pulvirenti, Francesco ,  Gariboldi, Roberto

IPC: G01R31/02 ,  G05B19/042

CPC classification number: G01R31/026 ,  G05B19/0423

公开(公告)号：EP1184962A1

公开(公告)日：2002-03-06

申请号：EP00830586.4

申请日：2000-08-22

Applicant: STMicroelectronics S.r.l. ,  TECDIS S.p.A.

Inventor： Gariboldi, Roberto ,  Lavorerio, Riccardo ,  Sala, Leonardo ,  Nidasio, Giovanni

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: This invention relates to a high-efficiency electronic circuit (1) for generating and regulating a supply voltage (Vout), comprising a charge-pump voltage multiplier (2) which is associated with an oscillator (3) and has an output connected to a voltage regulator (4) in order to ultimately output said supply voltage (Vout). Advantageously, the circuit comprises a first hysteresis comparator (5) having as inputs the regulator (4) output and the multiplier (2) output, and comprises a second hysteresis comparator (6) having as inputs a reference potential (Vrif) and a partition (K) of the voltage (Vout) presented on the regulator (4) output.
The comparators are structurally and functionally independent of each other, and their outputs are coupled to the oscillator (3) through a logic circuit (7) to modulate the oscillator (3) operation.

Abstract translation: 本发明涉及一种用于产生和调节的供给电压（Vout），其包括一个电荷泵电压倍增器的高效率电子电路（1）（2）所有其与在振荡器相关联的（3），并且具有对连接到输出 为了电压调节器（4），以最终所述输出电源电压（Vout）。 有利的是，该电路包括一个第一磁滞比较器（5），其具有作为输入的调节器（4）输出和乘法器（2）输出，和包括第二迟滞比较器（6），其具有作为输入的基准电势（Vrif）和分区 的电压的（K）（VOUT）呈现在调节器（4）输出。 比较器在结构上和功能上独立的海誓山盟，并且它们的输出通过一个逻辑电路（7）来调制所述振荡器（3）操作耦合到所述振荡器（3）。