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    A portable data substrate
    11.
    发明公开
    A portable data substrate 审中-公开
    Ein tragbarerDatenträger

    公开(公告)号：EP1204079A1

    公开(公告)日：2002-05-08

    申请号：EP00830730.8

    申请日：2000-11-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Fumagalli, Luciano ,  Rolandi, Pier Luigi

    IPC: G07F7/10 ,  G07C9/00 ,  G06K9/00

    CPC classification number: G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576 ,  G06Q20/40145 ,  G07C9/00087

    Abstract: A portable data substrate with protection against unauthorized access, comprising: a first non-volatile memory (11) containing protected data, a second non-volatile memory (17) containing identification data of at least one user authorized to have access to the protected data, means (12) for the input of personal data, and processing means (10) connected to the first memory, to the second memory, and to the input means in order to perform a procedure of identification and authorization for access to the protected data by a comparison between the personal data input and the identification data stored. Both the identification data and the personal data comprise data representing a fingerprint and the input means comprises a fingerprint sensor (12) which derives the personal data from a fingerprint of a finger applied to the sensor.

    Abstract translation: 一种具有防止未经授权的访问的便携式数据基板，包括：包含受保护数据的第一非易失性存储器（11），包含被授权访问受保护数据的至少一个用户的标识数据的第二非易失性存储器（17） ，用于输入个人数据的装置（12），连接到第一存储器的处理装置（10），第二存储器和输入装置，以执行用于访问受保护数据的识别和授权的过程 通过个人数据输入与存储的识别数据之间的比较。 识别数据和个人数据都包括表示指纹的数据，并且输入装置包括指纹传感器（12），其从施加到传感器的手指的指纹导出个人数据。

    Device for reading nonvolatile memory cells, in particular analog flash memory cells
    12.
    发明公开
    Device for reading nonvolatile memory cells, in particular analog flash memory cells 有权
    An ere ere ere en en en en en en en en en en en en en en en en en en en en

    公开(公告)号：EP0997912A1

    公开(公告)日：2000-05-03

    申请号：EP98830626.2

    申请日：1998-10-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Canegallo, Roberto ,  Guaitini, Giovanni ,  Rolandi, Pier Luigi

    IPC: G11C27/00 ,  G11C16/06 ,  G11C11/56

    CPC classification number: G11C16/34 ,  G11C7/16 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26 ,  G11C27/005 ,  G11C2211/5642

    Abstract: The reading device (1) comprises an A/D converter (8) of n+m bits receiving an input signal (V1) correlated to the threshold voltage (VTH) of the memory cell (2), and supplying a binary output word (WT) of n+m bits. The A/D converter (8) is of a double conversion stage type (8), wherein a first A/D conversion stage (10) carries out a first analog/digital conversion of the input signal (V1), to supply at the output a first intermediate binary word (W1) of n bits, and the second A/D conversion stage (16) can be activated selectively to carry out a second analog/digital conversion of a difference signal (VD) correlated to the difference between the input signal (V1) and the value of the first intermediate binary word (W1). The second A/D conversion stage (16) generates at the output a second intermediate binary word (W2) of m bits supplied, with the first intermediate binary word (W1), to an adder (20) generating the binary output word (WT) of n+m bits.

    Abstract translation: 读取装置（1）包括接收与存储单元（2）的阈值电压（VTH）相关的输入信号（V1）的n + m位的A / D转换器（8），并且提供二进制输出字 WT）n + m位。 A / D转换器（8）是双转换级（8），其中第一A / D转换级（10）执行输入信号（V1）的第一模/数转换，以在 输出n位的第一中间二进制字（W1），并且可以选择性地激活第二A / D转换级（16），以对与第一中间二进制字（W1）之间的差相关的差信号（VD）进行第二模/数转换 输入信号（V1）和第一中间二进制字（W1）的值。 第二A / D转换级（16）在输出端产生与第一中间二进制字（W1）一起提供的m位的第二中间二进制字（W2）到生成二进制输出字（WT）的加法器（20） ）n + m位。

    Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMs
    13.
    发明公开
    Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMs 失效
    对于中并行编程的非易失性存储设备，特别是闪存EEPROM的和方法

    公开(公告)号：EP0913835A1

    公开(公告)日：1999-05-06

    申请号：EP97830550.6

    申请日：1997-10-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Canegallo, Roberto ,  Chioffi, Ernestina ,  Pasotti, Marco ,  Gerna, Danilo ,  Rolandi, Pier Luigi

    IPC: G11C16/06

    CPC classification number: G11C16/3459 ,  G11C16/3454

    Abstract: The programming method comprises the steps of applying a programming pulse to a first cell (2) and simultaneously verifying the present threshold value of at least a second cell (2); then verifying the present threshold value of the first cell and simultaneously applying a programming pulse to the second cell. In practice, during the entire programming operation, the gate terminal of both the cells is biased to a same predetermined gate voltage (V PCX ) and the source terminal is connected to ground; the step of applying a programming pulse is carried out by biasing the drain terminal of the cell to a predetermined programming voltage (V P ) and the step OF verifying is carried out by biasing the drain terminal of the cell to a read voltage (V R ) different from the programming voltage. Thereby, switching between the step of applying a programming pulse and verifying is obtained simply by switching the drain voltage of the cells.

    Abstract translation: 该编程方法包括施加编程脉冲到第一小区（2），并同时验证至少一个第二小区（2）的本阈值的工序; 然后验证所述第一小区的当前阈值，并且同时施加编程脉冲到所述第二小区。 在实践中，整个编程操作期间，这两个单元的栅极端子被偏置到一个相同的栅极预定电压（VPCX）和源极端子连接到地; 施加编程脉冲的步骤是通过偏置单元的漏极端子至预定编程电压（VP）和检验步骤是通过偏置单元的漏极端子的读出电压（VR）不同开展开展 从编程电压。 由此，施加编程脉冲的步骤和验证之间的切换通过切换单元的漏极电压简单地获得。

    Programming method for a multilevel memory cell
    15.
    发明公开
    Programming method for a multilevel memory cell 有权
    Programmierverfahrenfüreine Multibitspeicherzelle

    公开(公告)号：EP1324342A1

    公开(公告)日：2003-07-02

    申请号：EP01830827.0

    申请日：2001-12-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Sandre, Guido ,  Poles, Marco ,  Iezzi, David ,  Pasotti, Marco

    IPC: G11C11/56

    CPC classification number: G11C11/5628 ,  G11C2211/5641

    Abstract: The invention relates to a programming method of a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), the method comprising at least a step of writing a logic value in the multilevel memory cell by setting one of the programming levels (LA) thereof, these levels being included in the plurality of levels (N), with respect to a reference level (LR) according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value (Lmax) for the levels (LS, LR) is reached.
    The invention relates also to a multilevel memory device comprising a plurality of multilevel memory cells organised into sectors, split into a plurality of data units (UD) whereon a programming operation is performed in parallel according to the method of the invention.

    Abstract translation: 本发明涉及能够存储多个电平（N）中的多个位的多电平存储器单元的编程方法，所述方法至少包括以下步骤：通过将所述多电平存储器单元 编程电平（LA），这些电平相对于根据要写入的符号的参考电平（LR）和先前的编程电平被包括在多个电平（N）中。 重复写入步骤直到达到电平（LS，LR）的最高可能值（Lmax）。 本发明还涉及一种多级存储器件，其包括被组织成扇区的多个多电平存储器单元，分成多个数据单元（UD），根据本发明的方法并行执行编程操作。

    Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method
    17.
    发明公开
    Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method 有权
    擦除和用于存储块并行重新写入电路，尤其是对于模拟快闪单元，和它们的操作

    公开(公告)号：EP1065668A1

    公开(公告)日：2001-01-03

    申请号：EP99830381.2

    申请日：1999-06-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Guaitini, Giovanni ,  Rolandi, Pier Luigi

    IPC: G11C16/08 ,  G11C8/00

    CPC classification number: G11C8/10 ,  G11C16/08

    Abstract: Circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, characterized in that it comprises at least one row decoding circuit (5, 7) comprising at least two adder blocks (31), suitable to generate a row address signal (32), at least two decoder blocks (33), suitable to generate respective pluralities of signals (34, 35, 36, 37; 42, 43, 44, 45) identifying a respective sector of memory to be enabled, at least two shifter blocks (38), suitable to generate an address signal (48, 49) of another row to be enabled, at least two OR logic blocks (39), suitable to generate respective signals (40; 41) serving the purpose to simultaneously enable at least two rows of the memory matrix (1).

    Abstract translation: 电路用于擦除和重写的存储单元和特别模拟闪存单元，在做了它包括至少一个行解码电路，其特征的块（5,7）包括至少两个加法器块（31），适合于生成的行地址信号（ 32），至少两个解码器块（33）适合于产生的信号（34，35，36，37 respectivement多个;启用识别的存储器中的扇区respectivement 42，43，44，45），至少两个移动器 块（38）适合于产生对另一行的地址信号（48，49）被使能，至少两个OR逻辑块（39）适于产生respectivement信号（40; 41）服务的目的为能够同时在 存储器矩阵的至少两排（1）。

    Column decoder for non-volatile memory devices, in particular of the phase-change type
    18.
    发明公开
    Column decoder for non-volatile memory devices, in particular of the phase-change type 有权
    SpaltendekodiererfürnichtflüchtigeSpeicher des Phasen-Übergangstyps

    公开(公告)号：EP2159802A1

    公开(公告)日：2010-03-03

    申请号：EP09168918.2

    申请日：2009-08-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Sandre, Guido ,  Pasotti, Marco

    IPC: G11C16/02 ,  G11C7/12 ,  G11C13/02

    CPC classification number: G11C13/0026 ,  G11C13/0004

    Abstract: Described herein is a column decoder (5) for a phase-change memory device (1; 1') provided with an array (2) of memory cells (3), a reading stage (6) for reading data contained in the memory cells (3), and a programming stage (7) for programming these data; the column decoder (5) selects and enables biasing of a bitline (BL) of the array (2) and generates a current path between the bitline (BL) and the reading stage (6; 6') or, alternatively, the programming stage (7), respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit (5a) generates a first current path between the bitline (BL) and the reading stage (6; 6'), and a second decoder circuit (5b), distinct and separate from the first decoder circuit (5a), generates a second current path, distinct from the first current path, between the bitline (BL) and the programming stage (7).

    Abstract translation: 这里描述了一种用于存储单元（3）阵列（2）的相变存储器件（1; 1'）的列解码器（5），用于读取包含在存储器单元 （3）和用于编程这些数据的编程阶段（7） 列解码器（5）选择并启用阵列（2）的位线（BL）的偏置，并产生位线（BL）和读取级（6; 6'）之间的电流路径，或者编程级 （7），分别在存储单元的内容的读取或编程操作期间。 在列解码器中，第一解码器电路（5a）产生位线（BL）和读取级（6; 6'）之间的第一电流路径，以及第二解码器电路（5b），其与第一解码器 电路（5a）在位线（BL）和编程级（7）之间生成与第一电流路径不同的第二电流路径。

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