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    A content addressable memory cell
    11.
    发明公开
    A content addressable memory cell 有权
    关于可选内容存储单元

    公开(公告)号：EP2261928A3

    公开(公告)日：2011-04-20

    申请号：EP10183801.9

    申请日：2003-10-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: G11C15/04 ,  G11C14/00

    CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    A content addressable memory cell
    12.
    发明公开
    A content addressable memory cell 有权
    内容可寻址存储单元

    公开(公告)号：EP2261928A2

    公开(公告)日：2010-12-15

    申请号：EP10183801.9

    申请日：2003-10-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: G11C15/04

    CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    Abstract translation: 一种用于非易失性内容可寻址存储器（100）的内容可寻址存储器单元（105），包括用于存储内容数字的非易失性存储装置（S1，S2，S），用于存储内容数字的选择输入（WLi; WLi，BLPj） 选择存储器单元，用于接收搜索数字（BLRj，BLLj）的搜索输入以及用于将搜索数字与内容数字进行比较并用于驱动存储器单元的匹配输出（MLi）以便发信号 内容数字和搜索数字之间的匹配。 非易失性存储装置包括至少一个用于以非易失性方式存储相应内容数字的相变存储器元件（S1，S2，S）。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby
    18.
    发明公开
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby 有权
    一种用于制备在铜镶嵌技术相变存储器阵列以及将相变存储器相应产生阵列处理

    公开(公告)号：EP1505656A1

    公开(公告)日：2005-02-09

    申请号：EP03425536.4

    申请日：2003-08-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto

    IPC: H01L27/24

    CPC classification number: H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells (33), arranged in rows and columns; and forming a plurality of resistive bit lines (35) for connecting PCM cells (33) arranged on a same column, each resistive bit lines (35) comprising a respective phase change material portion (31'), covered by a respective barrier portion (32'). After forming the resistive bit lines (35), electrical connection structures (45, 52) for the resistive bit lines (35) are formed directly in contact with the barrier portions (32') of the resistive bit lines (35).

    Abstract translation: 一种用于制造相变存储器阵列的方法，包括以下步骤：形成PCM单元的多个（33），以行和列布置; 以及形成电阻的位线用于连接PCM单元布置在同一列有多个（35）（33），每个电阻的位线（35），其包括respectivement相变材料部分（31“）中，由一个respectivement阻挡部分覆盖（ 32“）。 形成用于电阻的位线电阻的位线（35），电连接结构（45，52）之后，（35）直接与所述电阻的位线（35）的阻挡部分（32“）接触而形成。

    Process for manufacturing an array of cells including selection bipolar junction transistors
    19.
    发明公开
    Process for manufacturing an array of cells including selection bipolar junction transistors 有权
    用于与所述选择晶体管的双极电池装置和相关联的小区布置的制造方法

    公开(公告)号：EP1408549A1

    公开(公告)日：2004-04-14

    申请号：EP02425604.2

    申请日：2002-10-08

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Casagrande, Guilio ,  Gastaldi, Roberto ,  Vendrame, Loris ,  Benvenuti, Augusto ,  Lowrey, Tyler, c/o Ovonyx Inc.

    IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

    CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

    Abstract: A process for manufacturing an array of cells, including: implanting, in a body (10) of semiconductor material of a first conductivity type, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer (21) having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings (27a) with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions (14) of the first conductivity type; implanting second portions of the active area regions through the second openings (27b) with a doping agent of the second conductivity type, thereby forming control contact regions (15) of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components (3), each storage component having a terminal connected to a respective second conduction region (14).

    Abstract translation: 单元的阵列是通过注入第一导电类型，以通过绝缘层的第一开口有源区区域的第一部分的掺杂剂，以形成第二导电区制成; 注入第二导电类型到穿过绝缘层以形成控制接触区域的第二开口的有源区域的区域的第二部分中的掺杂剂; 和在所述主体的顶部上形成存储元件。 单元阵列的制造包括：提供第一导电类型的半导体材料的本体（10）; 植入在身体中，第一导电类型的公共导电区（11）; 形成在所述主体中，公共导电区域上方，有源区的区域的第二导电类型和第一掺杂水平的（12）; 形成，在所述主体的顶部，绝缘层上具有第一和第二开口（27A，27B）; 通过用第一导电类型的掺杂剂的第一开口注入所述有源区区域的第一部分，从而形成在所述有源区区域中的第一导电类型的第二传导区域; 通过注入与所述第二导电类型的掺杂剂的第二孔中的活性区域的区域的第二部分，所述第二导电类型和第二掺杂水平比所述第一掺杂等级高的形成，从而控制接触区域（15）; 并形成存储元件（24）在所述主体的顶部上。 每个控制接触区域形成，与所述第二传导区域和公共传导区，选择双极型晶体管（20）连接在一起。 每个存储组件具有连接到第二respectivement传导区的端子。 它定义，与双极晶体管，所述单元阵列的细胞一起。

    Architecture of a phase-change nonvolatile memory array
    20.
    发明公开
    Architecture of a phase-change nonvolatile memory array 有权
    建筑工人工程师协会

    公开(公告)号：EP1326254A1

    公开(公告)日：2003-07-09

    申请号：EP01830806.4

    申请日：2001-12-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Bosisio, Giorgio ,  Pellizzer, Fabio

    IPC: G11C11/34

    CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: The phase-change nonvolatile memory array (8) is formed by a plurality of memory cells (10, 10') extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines (11) extend parallel to the first direction. A plurality of word-selection lines (12) extend parallel to the second direction. Each memory cell (10, 10') includes a PCM storage element (15) and a selection transistor (16). A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line (12). A second terminal of the PCM storage element (15) is connected to a respective column-selection line (11), and a second terminal of the selection transistor (16) is connected to a reference-potential region (18) while reading and programming the memory cells (10, 10').

    Abstract translation: 相变非易失性存储器阵列（8）由在彼此正交的第一和第二方向上延伸的多个存储单元（10,10'）形成。 多个列选择线（11）平行于第一方向延伸。 多个字选择线（12）平行于第二方向延伸。 每个存储单元（10,10'）包括PCM存储元件（15）和选择晶体管（16）。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线（12）。 PCM存储元件（15）的第二端子连接到相应的列选择线（11），并且选择晶体管（16）的第二端子连接到参考电位区域（18），同时读取和编程 存储单元（10,10'）。

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