公开(公告)号：EP1811564A1

公开(公告)日：2007-07-25

申请号：EP06425025.1

申请日：2006-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Tortorelli, Innocenzo ,  Pirovano, Agostino ,  Bez, Roberto

IPC: H01L23/525 ,  G11C17/16 ,  H01L45/00

CPC classification number: H01L23/5256 ,  G11C13/0004 ,  G11C17/16 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Described herein is a fuse device (1) having a fuse element (2) provided with a first terminal (10) and a second terminal (16) and an electrically breakable region (15a), which is arranged between the first terminal (10) and the second terminal (16) and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal (10) from the second terminal (16). The electrically breakable region (15a) is of a phase-change material, in particular a calcogenic material, for example GST.

Abstract translation: 这里描述的是具有设置有第一端子（10）和第二端子（16）的熔丝元件（2）和电气断开区域（15a）的熔断器件（1） 和第二端子（16），并且被配置为由于提供编程电量而导致断开，从而将第一端子（10）与第二端子（16）电隔离。 电致断裂区域（15a）是相变材料，特别是钙质材料，例如GST。

公开(公告)号：EP1729303A1

公开(公告)日：2006-12-06

申请号：EP05104877.5

申请日：2005-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Pirovano, Agostino

IPC: G11C11/56

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/79

Abstract: A method and apparatus for programming a phase change memory cell (2) is disclosed. A phase change memory cell (2) includes a memory element (10) of a phase change material having a first state ("11"), in which the phase change material is crystalline and has a minimum resistance level, a second state ("00") in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states with resistance levels there between. The method includes using programming pulses to program the phase change memory cell (2) in either the set, reset, or one of the intermediate states. To program in the intermediate states, a programming pulse creates a crystalline percolation path having an average diameter (D) through amorphous phase change material and a second programming pulse modifies the diameter (D) of the crystalline percolation path to program the phase change memory cell to the proper current level.

公开(公告)号：EP1724851A1

公开(公告)日：2006-11-22

申请号：EP05020196.1

申请日：2005-09-16

Applicant: STMicroelectronics S.r.l.

Inventor： Conoci, Sabrina ,  Petralia, Salvatore ,  Sotgiu, Riccardo ,  Pirovano, Agostino

IPC: H01L51/00

CPC classification number: H01L51/0591 ,  B82Y10/00 ,  H01L51/0065 ,  H01L51/0067 ,  H01L51/0595 ,  H01L51/42 ,  Y10T428/24802

Abstract: Use of a fluorescein derivative having the following formula:

where Z + is an organic cation
for the production of a electronic device, in particular a memory switch.

Abstract translation: 使用具有下式的荧光素衍生物：其中Z +是用于生产电子器件的有机阳离子，特别是存储器开关。

公开(公告)号：EP1717861A1

公开(公告)日：2006-11-02

申请号：EP05425261.4

申请日：2005-04-27

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Pirovano, Agostino

IPC: H01L27/24 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7827 ,  G11C13/0004 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66666 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A vertical MOSFET transistor, formed in a body (13) of semiconductor material having a surface and housing a buried conductive region (19) of a first conductivity type; a channel region (29) of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region (26, 35c) of the first conductivity type, arranged on top of the channel region (29) and the buried conductive region (19); a gate insulation region (22), extending at the sides of and contiguous to the channel region (29); and a gate region (23, 35d) extending at the sides of and contiguous to the gate insulation region (22).

Abstract translation: 一种垂直MOSFET晶体管，形成在具有表面并且容纳第一导电类型的掩埋导电区域（19）的半导体材料的本体（13）中; 布置在所述掩埋导电区域的顶部上的第二导电类型的沟道区域（29）; 布置在沟道区域（29）和掩埋导电区域（19）的顶部上的第一导电类型的表面导电区域（26,35c）; 栅极绝缘区域（22），其在所述沟道区域（29）的两侧延伸; 以及在栅极绝缘区域（22）的侧面延伸并与栅极绝缘区域（22）相邻的栅极区域（23,35d）。