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    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC
    13.
    发明授权
    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC 失效
    生产含有非易失性存储器单元和至少两种不同类型的外围晶体管电路的方法，和相应的集成电路

    公开(公告)号：EP0751560B1

    公开(公告)日：2002-11-27

    申请号：EP95830282.0

    申请日：1995-06-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Clementi, Cesare ,  Ghidini, Gabriella ,  Riva, Carlo

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) including an intermediate dielectric multilayer comprising a lower silicon oxide layer (7), an intermediate silicon nitride layer (8) and an upper silicon oxide layer (10) and the simultaneous provision in zones peripheral to the memory cells of at least one first (2) and one second (3) transistor type having gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer (5) and a polycrystalline silicon layer (6) and the formation of the lower silicon oxide layer (7) and of the intermediate silicon nitride layer (8), the process in accordance with the present invention includes: removal of said layers from the zones peripheral (R2,R3) to the matrix; formation of a first silicon oxide layer (9) over the substrate in the areas (R2,R3) of both types of transistor (2,3); removal of the preceding layer (9) from areas (R3) assigned only to the transistors (3) of the second type; deposition of said upper silicon oxide layer (10) over the memory cells (1), over the first silicon oxide layer (9) in the areas (R2) of the transistors (2) of the first type and over the substrate (4) in the areas (R3) of the transistors of the second type; and formation of a second silicon oxide layer (11) in the areas (R2,R3) of both types of peripheral transistors (2,3).

    High voltage field-effect transistor and corresponding manufacturing method
    16.
    发明公开
    High voltage field-effect transistor and corresponding manufacturing method 失效
    Hochspannungsfeldeffekttransistor和Verfahren zu dessen Herstellung

    公开(公告)号：EP0928030A1

    公开(公告)日：1999-07-07

    申请号：EP97830744.5

    申请日：1997-12-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico ,  Riva, Carlo

    IPC: H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L21/336 ,  H01L27/088

    CPC classification number: H01L29/66575 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/7833

    Abstract: An HV transistor (2) integrated in a semiconductor substrate (1) with a first type of conductivity, comprising a gate region (12) included between corresponding drain (16) and source (17) regions, and being of the type wherein at least said drain region (16) is lightly doped with a second type of conductivity. The drain region (16) comprises a contact region (7) with the second type of conductivity but being more heavily doped, from which a contact pad (21) stands proud.

    Abstract translation: 集成在具有第一类型导电性的半导体衬底（1）中的HV晶体管（2）包括在相应的漏极（16）和源极（17）区域之间包括的栅极区域（12），并且是至少 所述漏极区域（16）被轻掺杂第二类导电性。 漏极区域（16）包括具有第二类导电性但是更重掺杂的接触区域（7），接触垫（21）从该接触区域引出。

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