公开(公告)号：EP1367597A1

公开(公告)日：2003-12-03

申请号：EP02425360.1

申请日：2002-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Camerlenghi, Emilio ,  Cappelletti, Paolo ,  Ghilardi, Tecla ,  Sali, Mauro ,  Servalli, Giorgio

IPC: G11C29/00

CPC classification number: G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

Abstract: The present invention relates to an improved integrated non-volatile memory device including a matrix of cells organised into rows, or word lines, and columns, or bit lines, and including corresponding row and column decoding circuits as well as read, modify and erase circuits for reading and modifying data stored in the memory cells. Advantageously, the integrated memory device comprises test structure (2) including a smaller second matrix (3) of cells comprising couples of word lines (WL) each having a difference contact to gate distance.
Each couple of word lines is gradually misaligned from each adjacent couple of word lines by a distance that is variable from couple to couple.
This proposed structure allows monitoring with a large statistic one of the most critical technology parameter for FLASH reliability.

Abstract translation: 本发明涉及改进的集成的非易失性存储器装置，其包括组织为行的细胞，或字线，和列，或位线，的一个矩阵和包括对应的行和列解码电路以及读，修改和擦除电路 用于读取和修改存储在所述存储器单元中的数据。 有利地，所述集成的存储器装置包括测试结构（2）包括包含细胞的字线（WL）每一个都具有差接触到栅极距离耦合的较小的第二矩阵（3）。 每一对字线被从每个相邻的一对字线的距离逐渐错开确实是从耦合到耦合变量。 此提议的结构允许具有大统计量技术FLASH可靠性的最关键参数之一的监测。

公开(公告)号：EP1816675A1

公开(公告)日：2007-08-08

申请号：EP06425059.0

申请日：2006-02-03

Applicant: STMicroelectronics S.r.l.

Inventor： Costantini, Sonia ,  Pavan, Alessia ,  Servalli, Giorgio

IPC: H01L21/8247 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L27/11539 ,  H01L27/11543 ,  H01L27/11546

Abstract: Process for manufacturing a non volatile memory electronic device (2) integrated on a semiconductor substrate (1) which comprises a matrix of non volatile memory cells (4), said memory cells (4) organised in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors (3), comprising the steps of:
- forming, by means of a photo-lithographic process which provides the use of a first photo-lithographic mask, gate electrodes (12) of the high voltage transistors (3) projecting from a first portion (A) of the semiconductor substrate (1).
- forming first spacers (15) on the side walls of the gate electrodes (12) of said high voltage transistors (3) of a first length (L1),
- forming, by means of a photo-lithographic process which provides the use of a second photo lithographic mask which covers said high voltage transistors (3), gate electrodes (16) of said memory cells (4) projecting from a second portion (B) of said semiconductor substrate (1), each of said gate electrodes (16) of memory cells (4) comprising a floating gate electrode (FG) and a control gate electrode (CG)

Abstract translation: 一种集成在半导体衬底（1）上的非易失性存储器件（2）的制造方法，该半导体衬底（1）包括非易失性存储器单元（4）的矩阵，所述存储单元（4）被组织成行，称为字线和列， 所谓的位线和包括高压晶体管（3）的相关电路，包括以下步骤： - 通过提供使用第一光刻掩模的光刻工艺，形成所述第一光刻掩模的栅电极（12） 从半导体衬底（1）的第一部分（A）伸出的高电压晶体管（3）。 - 在第一长度（L1）的所述高压晶体管（3）的栅极（12）的侧壁上形成第一间隔物（15）， - 通过光刻工艺形成，所述光刻工艺提供使用 覆盖所述高压晶体管（3）的第二光刻掩模，从所述半导体衬底（1）的第二部分（B）突出的所述存储单元（4）的栅电极（16），每个所述栅电极 ）包括浮栅电极（FG）和控制栅电极（CG）的存储单元（4）

公开(公告)号：EP1804293A1

公开(公告)日：2007-07-04

申请号：EP05425942.9

申请日：2005-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Servalli, Giorgio ,  Carollo, Enzo

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/764 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/3011

Abstract: Process for manufacturing a non volatile electronic device integrated on a semiconductor substrate (2) which comprises a plurality of non volatile memory cells (1) being organised in matrix and an associated circuitry, comprising the steps of:
- forming gate electrodes (7) of the memory cells (1) projecting from the semiconductor substrate (2), each of the gate electrodes (7) comprising a first dielectric layer (3), a floating gate electrode (4), a second dielectric layer (5) and a control gate electrode (6) coupled to a respective word line, at least one first portion of the gate electrodes (7) of the memory cells (1) being separated from each other by first openings (15) of a first width (D),
- forming source and drain regions (8) of the memory cells (1) in the semiconductor substrate (2), the source and drain regions (8) of the memory cells (1) being aligned with the gate electrodes (7) of the memory cells (1),
- forming gate electrodes of transistors of the circuitry projecting from the semiconductor substrate (2), each of the gate electrodes of the circuitry comprising a first dielectric layer of the circuitry and a first conductive layer of the circuitry,
- forming source and drain regions of the transistors in the semiconductor substrate (2), the source and drain regions of the transistors being aligned with the gate electrodes (7) of the transistors, the process being characterised in that it comprises the following steps:

- depositing, on the whole device, a third non conform dielectric layer (10) so as to completely fill in the first openings (15) and to form air-gaps (16) between the gate electrodes belonging to the first portion of the gate electrodes (7) of the memory cells (1).

Abstract translation: 一种用于制造集成在半导体衬底（2）上的非易失性电子器件的方法，该半导体衬底包括以矩阵形式组织的多个非易失性存储器单元（1）和相关联的电路，包括以下步骤： - 形成栅电极 从半导体衬底（2）突出的存储单元（1），每个栅电极（7）包括第一介电层（3），浮栅电极（4），第二介电层（5）和控制 栅极电极（6），其耦合到相应的字线，存储单元（1）的栅电极（7）的至少一个第一部分通过第一宽度（D）的第一开口（15）彼此分开， - 在所述半导体衬底（2）中形成所述存储单元（1）的源区和漏区（8），所述存储单元（1）的源区和漏区（8）与所述半导体衬底 存储单元（1）， - 形成所述电路的晶体管的栅电极 在所述半导体衬底（2）中，所述电路的每个栅电极包括所述电路的第一介电层和所述电路的第一导电层， - 形成所述半导体衬底（2）中的所述晶体管的源区和漏区， 晶体管的源极和漏极区域与晶体管的栅电极（7）对准，该工艺的特征在于其包括以下步骤： - 在整个器件上沉积第三非标准电介质层（10） 以便完全填充第一开口（15）并且在属于存储单元（1）的栅电极（7）的第一部分的栅电极之间形成气隙（16）。

公开(公告)号：EP1804289A2

公开(公告)日：2007-07-04

申请号：EP06026787.9

申请日：2006-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Servalli, Giorgio ,  Capetti, Gianfranco ,  Cantú, Pietro

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11521

Abstract: A non volatile memory device is described being integrated on semiconductor substrate (11, 110) and comprising a matrix of non volatile memory cells (12, 120) organised in rows, called word lines, and columns, called bit lines, the device comprising:
- a plurality of active areas (13, 130) formed on the semiconductor substrate (11, 110) comprising a first and a second group (G1, G2; G3, G4) of active areas,
- the non volatile memory cells (12, 120) being integrated in the first group (G1, G3) of active areas, each non volatile memory cell (12, 120) comprising a source region, a drain region and a floating gate electrode coupled to a control gate electrode, at least one group (14, 140) of the memory cells (12, 120) sharing a common source region (15, 150) integrated on the semiconductor substrate (11, 110), the device being characterised in that:

- said plurality of active areas (13, 130) are equidistant from each other,
- a contact region (16, 160) is integrated in the second group (G2, G4) of active areas (13, 130) and is provided with at least one common source contact (17, 170) of said common source region (15, 150).

Abstract translation: 描述了非易失性存储器件集成在半导体衬底（11,110）上，并且包括被称为位线的称为字线的行的非易失性存储器单元（12,120）的矩阵，所述器件包括： - 形成在半导体衬底（11,110）上的多个有源区（13,130），包括有源区的第一和第二组（G1，G2; G3，G4）， - 非易失性存储单元（12， 120）集成在有源区的第一组（G1，G3）中，每个非易失性存储单元（12,120）包括耦合到控制栅极的源极区，漏极区和浮栅，至少一个 所述存储单元（12,120）的组（14,140）共享共同的半导体衬底（11,110）上的公共源极区域（15,150），所述器件的特征在于： - 所述多个有源区域 13,130）彼此等距， - 接触区域（16,160）被集成在第二组（G2 ，G4）的有源区域（13,130），并且设置有所述公共源极区域（15,150）的至少一个公共源极触点（17,170）。

公开(公告)号：EP1367597B1

公开(公告)日：2005-08-03

申请号：EP02425360.1

申请日：2002-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Camerlenghi, Emilio ,  Cappelletti, Paolo ,  Ghilardi, Tecla ,  Sali, Mauro ,  Servalli, Giorgio

IPC: G11C29/00

CPC classification number: G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

公开(公告)号：EP1403909A1

公开(公告)日：2004-03-31

申请号：EP02425586.1

申请日：2002-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Grossi, Alessandro ,  Bez, Roberto ,  Servalli, Giorgio

IPC: H01L21/02 ,  H01L27/08

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: A process for the fabrication of integrated resistive elements with protection from silicidation envisages the steps of: delimiting, in a semiconductor wafer (10), at least one active area (15); and forming, in the active area (15) at least one resistive region (21) having a pre-determined resistivity. Prior to forming the resistive region (21), on top of the active area (15) a delimitation structure (20) for delimiting the resistive region (21) is obtained, and, subsequently, protective elements (25), which extend within the delimitation structure (20) and coat the resistive region (21), are obtained.

Abstract translation: 集成电阻器通过在半导体晶片（10）中限定至少一个有效区域来制造; 以及在所述有源区域中形成具有预设电阻率的电阻区域。 在有源区域的顶部，形成用于限定电阻区域的定界结构。 获得了在限定结构内延伸并覆盖电阻区域的保护元件。