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    High-efficiency regulated voltage-boosting device
    15.
    发明公开
    High-efficiency regulated voltage-boosting device 审中-公开
    Hocheffiziente regulierteSpannungserhöhungsvorrichtung

    公开(公告)号：EP1298777A1

    公开(公告)日：2003-04-02

    申请号：EP01830613.4

    申请日：2001-09-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pulvirenti, Francesco ,  Bontempo, Gregorio

    IPC: H02M3/07 ,  G09G3/36

    CPC classification number: H02M3/073 ,  G09G3/36 ,  G09G3/3696 ,  G09G2330/02 ,  G09G2330/021 ,  H02M2001/0022 ,  Y10T307/747

    Abstract: A regulated voltage-boosting device including a charge-pump circuit (11), which has an input terminal (4a) receiving a first voltage (V DD ) and an output terminal (4b) supplying a second voltage (V LCD ) higher than said first voltage (V DD ), and being provided with a plurality of voltage-boosting stages (17) that can be selectively activated and deactivated. The regulated voltage-boosting device moreover comprises an automatic-selection circuit (10) for activating a number of voltage-boosting stages (17) which is correlated to the first voltage (V DD ) and to the second voltage (V LCD ).

    Abstract translation: 一种包括电荷泵电路（11）的稳压升压装置，其具有接收第一电压（VDD）的输入端（4a）和提供高于所述第一电压（VDD）的第二电压（VLCD）的输出端（4b） （VDD），并且设置有可以选择性地激活和去激活的多个升压级（17）。 调节升压装置还包括用于激活与第一电压（VDD）和第二电压（VLCD）相关的多个升压级（17）的自动选择电路（10）。

    Circuit architecture for performing a trimming operation on integrated circuits
    16.
    发明公开
    Circuit architecture for performing a trimming operation on integrated circuits 有权
    Schaltungsarchitektur zur Trimmung von integrierten Schaltungen

    公开(公告)号：EP1211516A1

    公开(公告)日：2002-06-05

    申请号：EP00830795.1

    申请日：2000-11-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Signorelli, Tiziana ,  Pulvirenti, Francesco ,  Ribellino, Calogera

    IPC: G01R31/30 ,  G06F11/00

    CPC classification number: G06F11/006 ,  H01L2223/5444

    Abstract: The invention relates to a circuit architecture and a relevant method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture of this invention comprises at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a means (17,19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from the normal mode over to the trimming mode. This circuit architecture further comprises a volatile memory unit (2) associated with the non-volatile memory unit (3) for storing up the non-volatile memory (3) state at power-on or at the simulating phase, and storing up the sequence (25) of trimming data at the programming phase; an interface (6) is provided between said pins (7,8,9) and the memory unit (2,3) for initially storing the data sequence (25) into the volatile memory unit and subsequently timing the trimming operation.

    Abstract translation: 本发明涉及一种用于在应用板上直接执行修整操作，或者在封装集成电子设备的操作之后的相关方法。 本发明的电路架构包括至少一个具有非易失性存储元件（5）的非易失性存储器单元（3）和用于修改存储元件（5）的状态的装置（17,19），第一多功能 接收修剪数据的序列（25）的输入引脚（8），接收修整操作的定时信号的第二多功能输入引脚（9），以及用于切换电路架构操作的附加接入引脚（7） 从正常模式切换到修剪模式。 该电路架构还包括与非易失性存储器单元（3）相关联的易失性存储器单元（2），用于在上电或模拟阶段存储非易失性存储器（3）状态，并存储该序列 （25）在编程阶段修整数据; 在所述引脚（7,8,9）和存储器单元（2,3）之间提供接口（6），用于将数据序列（25）初始地存储到易失性存储器单元中，并且随后对修整操作进行定时。

    Integrated circuit generating at least a voltage linear ramp having a slow rise
    17.
    发明公开
    Integrated circuit generating at least a voltage linear ramp having a slow rise 有权
    具有小节距的至少一个电压的线性斜坡产生集成电路

    公开(公告)号：EP1017172A1

    公开(公告)日：2000-07-05

    申请号：EP98830792.2

    申请日：1998-12-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ribellino, Calogero ,  Milazzo, Patrizia ,  Pulvirenti, Francesco

    IPC: H03K4/02 ,  H03K17/16

    CPC classification number: H03K17/163 ,  H03K4/023

    Abstract: Integrated circuit (20, 80, 90) generating at least a voltage linear ramp having a slow rise of the type comprising an input terminal (21, 81, 91), connected to a first voltage reference (VREF) and an output terminal (24, 84, 94) adapted for providing a controlled ramp signal (V RAMP ), the circuit comprising at least one operational amplifier (OP3) having a non-inverting input terminal connected to said input terminal (21, 81, 91) and to an output terminal in feedback on an inverting input terminal and connected to the output terminal (24, 84, 94) of the ramp generator circuit (20, 80, 90) itself.
    The ramp voltage generator (20, 80, 90) according to the invention further comprises a first storage capacitance (Cs) connected between the non-inverting input terminal of the operational amplifier (OP3) and a ground voltage reference (GND) and loaded by means of a second pumping capacitance (Cp) inserted in parallel to said first capacitance (Cs) between the input terminal (21, 81, 91) of the ramp generator circuit (20, 80, 90) and the ground voltage reference (GND).

    Abstract translation: 集成电路（20，80，90）至少产生具有包括输入端子（21，81，91）的连接到第一参考电压（VREF）的类型的缓慢上升的电压线性斜坡和输出端子（24 （84，94）用于angepasst提供受控斜坡信号VRAMP），所述电路包括至少一个运算放大器（OP3），其具有连接到所述输入端子（21，81，91的非反相输入端子），并向输出 终端反馈到反相输入端和连接到斜坡发生器电路（20，80，90）本身的输出端（24，84，94）。 斜坡电压发生器（20，80，90）雅丁到本发明还包括连接在所述运算放大器（OP3）的非反相输入端之间的第一存储电容（Cs）等的接地参考电压（GND），并加载由 斜坡发生器电路（20，80，90）与接地电压参考的输入端（21，81，91）之间插入在平行于所述第一电容（Cs）的第二泵浦电容（CP）的装置（GND） ，

    A circuit for detecting digital signals, particularly for a system with an ASI field bus
    18.
    发明公开
    A circuit for detecting digital signals, particularly for a system with an ASI field bus 有权
    Schaltung zur digitalen Signalerkennung insbesonderefürSystem mit ASI-Feldbus

    公开(公告)号：EP1001506A1

    公开(公告)日：2000-05-17

    申请号：EP98830672.6

    申请日：1998-11-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pulvirenti, Francesco ,  Bontempo, Gregorio ,  Palumbo, Gaetano

    IPC: H02J13/00

    CPC classification number: H02J13/0003

    Abstract: A circuit for detecting signals present on a bifilar voltage-supply and signal-transmission line, in which the signals are constituted by positive and negative variations of the supply potential of at least one of the wires of the line (2), comprises: a low-pass filter (20) connected to the two wires of the line in order to supply, at an output terminal of the filter, a constant reference potential (V+) substantially equal to the supply potential of a preselected one of the two wires, a first threshold comparator (21) having a reference input terminal (27) and a threshold input terminal (29) connected, respectively, to the output terminal (18) of the filter (20) and to the preselected wire of the two wires, and a second threshold comparator (22) having a reference input terminal (28) and a threshold input terminal (30) connected, respectively, to the preselected wire of the two wires and to the output terminal (18) of the filter (20).
    The circuit is relatively simple, does not require synchronization signals, and can be formed as an integrated circuit, taking up a limited area.

    Abstract translation: 用于检测出现在双向电压和信号传输线上的信号的电路，其中信号由线（2）的至少一根电线的供电电位的正和负变化构成，包括： 低通滤波器（20）连接到线路的两条线，以便在滤波器的输出端处提供基本上等于两条线中预选的电源的电位的恒定参考电位（V +）， 具有参考输入端子（27）和阈值输入端子（29）的第一阈值比较器（21）分别连接到滤波器（20）的输出端子（18）和两根导线的预选导线， 以及具有参考输入端子（28）和阈值输入端子（30）的第二阈值比较器（22）分别连接到两根导线的预选导线和滤波器（20）的输出端子（18） 。 电路比较简单，不需要同步信号，可以形成集成电路，占用有限的区域。

    Control circuit for the current switch edges of a power transistor
    19.
    发明公开
    Control circuit for the current switch edges of a power transistor 失效
    Steuerschaltungfürdie Strom-Schalt-Flanken eines Leistungstransistors

    公开(公告)号：EP0881770A1

    公开(公告)日：1998-12-02

    申请号：EP97830258.6

    申请日：1997-05-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pulvirenti, Francesco ,  Milazzo, Patrizia

    IPC: H03K17/16 ,  H02J7/10

    CPC classification number: H02J7/0052 ,  H03K4/00 ,  H03K17/163

    Abstract: A battery-charging electronic device comprises a current generator (2) adapted to supply a charging current to a battery (3) and a controlled current edge switch having a circuit (1) for controlling the switching edges of current (I O ) being flowed through a power transistor (PW).
    The switching edge control circuit (1) comprises:

    a controlled edge variable voltage generator for generating a controlled edge voltage signal (VA);
    a voltage/current converter (11) for converting the voltage signal (VA) to a controlled edge current signal (I R );
    a driver circuit (12) for the power transistor (PW) being input the controlled edge current signal (I R ) to mirror, onto the power transistor (PW), an output current (I O ) which is proportional to the controlled edge current signal (I R ).

    Abstract translation: 电池充电电子设备包括适于向电池（3）提供充电电流的电流发生器（2）和具有用于控制电流（IO）的开关边缘流过的电路（1）的受控电流边缘开关） 功率晶体管（PW）。 开关边缘控制电路（1）包括：用于产生受控边沿电压信号（VA）的受控边缘可变电压发生器; 用于将电压信号（VA）转换为受控边沿电流信号（IR）的电压/电流转换器（11）; 用于功率晶体管（PW）的驱动器电路（12）将受控边沿电流信号（IR）输入到功率晶体管（PW）上以反映与受控边沿电流信号成比例的输出电流（IO） IR）。

    Analogic MPPT circuit for photovoltaic power generation plant
    20.
    发明公开
    Analogic MPPT circuit for photovoltaic power generation plant 审中-公开
    Analogische MPPT-SchaltungfürPhotovoltaische Stromerzeugungsanlage

    公开(公告)号：EP2290784A2

    公开(公告)日：2011-03-02

    申请号：EP10166273.2

    申请日：2010-06-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ruà, Francesco ,  Privitera, Salvatore Giuseppe ,  Signorelli, Tiziana Teresa ,  Pulvirenti, Francesco

    IPC: H02J7/35 ,  G05F1/67

    CPC classification number: H02J7/35 ,  Y02E10/566 ,  Y02E10/58 ,  Y10T307/593

    Abstract: An outstandingly effective method of maximum power point tracking (MPPT) in operating a photovoltaic power plant that includes at least a DC-DC converter of the output voltage ( V PV ) of a single panel or of a plurality of series-parallel interconnected panels, having a power switch driven by a PWM control signal ( V PWM ) of variable duty-cycle (D) generated by a PWM control circuit, in discontinuous conduction mode (DCM) or continuous conduction mode (CCM) depending on the current load of the converter, is implemented by simple low cost analog circuits. The method does not require the use of any analog to digital conversion, digital processing or storage resources and requires only a single voltage sensor, in other words, no dissipative sensing resistance needs to be introduced.

    Abstract translation: 一种用于操作光伏发电厂的最大功率点跟踪（MPPT）的非常有效的方法，该光伏发电厂至少包括单个面板或多个串并联互连面板的输出电压（V PV）的DC-DC转换器， 具有由PWM控制电路产生的可变占空比（D）的PWM控制信号（V PWM）驱动的电力开关，其具有不连续导通模式（DCM）或连续导通模式（CCM），这取决于电流负载的当前负载 转换器，由简单的低成本模拟电路实现。 该方法不需要使用任何模数转换，数字处理或存储资源，并且仅需要单个电压传感器，换句话说，不需要引入耗散的感测电阻。

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