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    Phase-change memory device with biasing of deselected bit lines
    11.
    发明公开
    Phase-change memory device with biasing of deselected bit lines 有权
    Ph en en en en en en en en en en en en en en en en en en en

    公开(公告)号：EP1511042A1

    公开(公告)日：2005-03-02

    申请号：EP03077667.8

    申请日：2003-08-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bedeschi, Ferdinando ,  Resta, Claudio

    IPC: G11C11/34

    CPC classification number: G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

    Abstract: A memory device (100) is proposed. The memory device includes a matrix (105) of memory cells (P h,k ,T h,k ) arranged in a plurality of rows and a plurality of columns, each memory cell including a functional element (P h,k ) with a programmable resistivity and a unidirectional conduction access element (T h,k ) connected in series, a plurality of word lines (WL h ) and a plurality of bit lines (BL k ), the memory cells of each row being connected to a corresponding word line and the memory cells of each column being connected to a corresponding bit line, means (120) for driving the bit lines to a desired voltage, means (110c,115) for selecting at least one bit line in an operative condition of the memory device, each selected bit line being connected to the means for driving and each deselected bit line being disconnected from the means for driving, and means (110r) for selecting a word line in the operative condition, each access element associated with the selected word line and the at least one selected bit line being forward biased and the other access elements being reverse biased; the memory device further includes means (Pd h ,Td h ;B k ,Bd,205,S k ,Sd;D k ,Dd,303-320) for biasing the deselected bit lines in the operative condition to prevent a leakage current of the reverse biased access elements from forward biasing the access elements associated with the selected word line and the deselected bit lines.

    Abstract translation: 提出了一种存储装置（100）。 存储器件包括排列成多行和多列的存储单元（Ph，k，Th，k）的矩阵（105），每个存储单元包括具有可编程电阻率的功能元件（Ph，k） 串行连接的单向导通接入元件（Th，k），多个字线（WLh）和多个位线（BLk），每行的存储单元连接到相应的字线，并且存储单元 每列连接到对应的位线，用于将位线驱动到期望电压的装置（120），用于在存储器件的操作状态中选择至少一个位线的装置（110c，115），每个选择的位线 连接到用于驱动的​​装置和每个取消选择的位线与用于驱动的​​装置断开;以及用于在操作状态中选择字线的装置（110r），与所选择的字线和所选择的至少一个所选择的字线相关联的每个存取元件 位线正向b 其他访问元素被反向偏移; 存储器件还包括用于在操作状态下偏置未选位线的装置（Pdh，Tdh; Bk，Bd，205，Sk，Sd; Dk，Dd，303-320），以防止反向偏置访问元件 从正向偏置与所选择的字线和取消选择的位线相关联的存取元件。

    Phase change memory device with overvoltage protection and method for protecting a phase change memory device against overvoltages
    15.
    发明公开
    Phase change memory device with overvoltage protection and method for protecting a phase change memory device against overvoltages 有权
    相变存储器以浪涌保护和保护方法，用于相变存储器与浪涌保护

    公开(公告)号：EP1538632A1

    公开(公告)日：2005-06-08

    申请号：EP03425728.7

    申请日：2003-11-12

    Applicant: STMicroelectronics S.r.l. ,  Universita' Degli Studi Di Pavia

    Inventor： Bedeschi, Ferdinando ,  Resta, Claudio ,  Torelli, Guido

    IPC: G11C11/34 ,  G11C7/12

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0059 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: A phase change memory device includes a plurality of PCM cells (3), arranged in rows and columns, PCM cells (3) arranged on the same column being connected to a same bit line (10); a plurality of first selectors (12), each coupled to a respective PCM cell (3); an addressing circuit (4, 5) for selectively addressing at least one of the bit lines (10), one of the first selectors (12), and the PCM cell (3) connected to the addressed bit line (10) and to the addressed first selector (12); and a regulated voltage supply circuit (7, 14, 15), selectively connectable to the addressed bit line (10), for supplying a bit line voltage (V BL ). The bit line voltage (V BL ) is correlated to a first control voltage (V EBA ) on the addressed first selector (12), coupled to the addressed PCM cell (3).

    Abstract translation: 一种相变存储器装置包括PCM单元的多个（3），以行和列布置，PCM单元（3）布置在相同的列被连接到相同的位线（10）; 第一选择器的多个（12），每个耦合到respectivement PCM单元（3）; 在用于选择性地寻址所述位线中的至少一个（10）中，第一选择器中的一个（12）和所述PCM单元寻址电路（4,5）（3）连接到所寻址的位线（10）和所述 寻址第一选择器（12）; 和经调节的电压供给电路（7，14，15）选择性地连接到用于供给位线电压（VBL）被寻址的位线（10）。 位线电压（VBL）被关联以在被寻址第一选择器（12），耦合到所寻址的PCM单元（3）的第一控制电压（VEBA）。

    Architecture of a phase-change nonvolatile memory array
    16.
    发明公开
    Architecture of a phase-change nonvolatile memory array 有权
    建筑工人工程师协会

    公开(公告)号：EP1326254A1

    公开(公告)日：2003-07-09

    申请号：EP01830806.4

    申请日：2001-12-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Bosisio, Giorgio ,  Pellizzer, Fabio

    IPC: G11C11/34

    CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: The phase-change nonvolatile memory array (8) is formed by a plurality of memory cells (10, 10') extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines (11) extend parallel to the first direction. A plurality of word-selection lines (12) extend parallel to the second direction. Each memory cell (10, 10') includes a PCM storage element (15) and a selection transistor (16). A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line (12). A second terminal of the PCM storage element (15) is connected to a respective column-selection line (11), and a second terminal of the selection transistor (16) is connected to a reference-potential region (18) while reading and programming the memory cells (10, 10').

    Abstract translation: 相变非易失性存储器阵列（8）由在彼此正交的第一和第二方向上延伸的多个存储单元（10,10'）形成。 多个列选择线（11）平行于第一方向延伸。 多个字选择线（12）平行于第二方向延伸。 每个存储单元（10,10'）包括PCM存储元件（15）和选择晶体管（16）。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线（12）。 PCM存储元件（15）的第二端子连接到相应的列选择线（11），并且选择晶体管（16）的第二端子连接到参考电位区域（18），同时读取和编程 存储单元（10,10'）。

    Single supply voltage, nonvolatile memory device with cascoded column decoding
    17.
    发明公开
    Single supply voltage, nonvolatile memory device with cascoded column decoding 审中-公开
    NichtflüchtigeSpeicheranordnung mit einziger Speisespannung mit Kaskode-Spaltendekodiererung

    公开(公告)号：EP1324345A1

    公开(公告)日：2003-07-02

    申请号：EP01830808.0

    申请日：2001-12-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando

    IPC: G11C16/24

    CPC classification number: G11C13/0026 ,  G11C7/22 ,  G11C13/0038 ,  G11C16/24 ,  G11C2216/22

    Abstract: A nonvolatile memory device (1') is described comprising a memory array (2), a row decoder (3) and a column decoder (4) for addressing the memory cells (7) of the memory array (2), and a biasing stage (13,19) for biasing the drain terminal of the addressed memory cell (7). The biasing stage (13,19) is coupled between the column decoder (4) and the memory array (2) and comprises a biasing transistor (13) having a drain terminal connected to the column decoder (4), a source terminal connected to the drain terminal of the addressed memory cell (7), and a gate terminal receiving a driving signal of a logic type, the logic levels whereof are defined by precise and stable voltages and are generated by a first driving circuit (19) formed by a driving stage (20) and a buffer (21), cascade-connected.

    Abstract translation: 描述了一种非易失性存储器件（1'），其包括用于寻址存储器阵列（2）的存储器单元（7）的存储器阵列（2），行解码器（3）和列解码器（4） （13,19），用于偏置寻址的存储单元（7）的漏极端子。 偏置级（13,19）耦合在列解码器（4）和存储器阵列（2）之间，并且包括偏置晶体管（13），其漏极端子连接到列解码器（4），源极端子连接到 所述寻址的存储单元（7）的漏极端子和接收逻辑类型的驱动信号的栅极端子，其逻辑电平由精确和稳定的电压限定，并由由第一驱动电路（19）形成的第一驱动电路 驱动级（20）和缓冲器（21），级联。

    Method and device for irreversibly programming and reading nonvolatile memory cells
    18.
    发明公开
    Method and device for irreversibly programming and reading nonvolatile memory cells 审中-公开
    方法和装置用于非易失性存储器单元的不可逆编程和读取

    公开(公告)号：EP2045814A1

    公开(公告)日：2009-04-08

    申请号：EP07425616.5

    申请日：2007-10-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio

    IPC: G11C16/02 ,  G11C16/10 ,  G11C17/14 ,  G11C16/26

    CPC classification number: G11C13/0069 ,  G11C11/005 ,  G11C11/5678 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0078

    Abstract: In a nonvolatile memory device, data stored in a memory cell (21a, 21b) are associated to whether or not the memory cell is switchable between a first state and a second state. Memory cells are irreversibly programmed by applying an irreversible programming signal (I IRP ), such that the nonvolatile memory cells (21a) are made not switchable between the first state and the second state in response to the irreversible programming signal (I IRP ). Reading memory cells includes: assessing (100, 110, 120, 140, 150, 160) whether a memory cell (21a, 21b) is switchable between a first state and a second state; determining that a first irreversible logic value ("1") is associated to the memory cell (21a), if the memory cell (21a) is not switchable between the first state and the second state (130); and determining that a second irreversible logic value ("0") is associated to the memory cell (21b), if the memory cell (21b) is switchable between the first state and the second state (170).

    Abstract translation: 在非易失性存储器装置中，存储在存储器单元中的数据（21A，21B）被关联到所述存储器单元是否为第一状态和第二状态之间切换。 存储单元通过施加不可逆编程信号（I IRP）不可逆编程，检查做了非易失性存储单元（21a）的由响应于不可逆编程信号（I IRP）的第一状态和所述第二状态之间不切换。 读取存储器单元包括：评估（100，110，120，140，150，160）是否存储单元（21A，21B）为第一状态和第二状态之间切换; 确定性挖掘做了第一不可逆逻辑值（“1”）关联到所述存储单元（21a），如果存储单元（21a）没有所述第一状态和所述第二状态（130）之间切换; 和确定性挖掘做了第二不可逆逻辑值（“0”）被关联到所述存储单元（21B），如果存储单元（21B）是在第一状态和第二状态（170）之间切换。

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