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    A method of manufacturing an integrated circuit with MOS transistors having high breakdown voltages, and with precision resistors
    11.
    发明公开
    A method of manufacturing an integrated circuit with MOS transistors having high breakdown voltages, and with precision resistors 失效
    制造工艺与精密电阻高击穿电压的MOS晶体管的集成电路

    公开(公告)号：EP0880165A1

    公开(公告)日：1998-11-25

    申请号：EP97830230.5

    申请日：1997-05-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Stucchi, Elena ,  Daffra, Stefano ,  Cereda, Manlio Sergio

    IPC: H01L21/00 ,  H01L21/329 ,  H01L21/8234

    CPC classification number: H01L28/20 ,  H01L21/8234 ,  H01L27/0629 ,  H01L29/66166 ,  H01L29/8605

    Abstract: The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips (14) for constituting the gate electrodes of the MOS transistors and portions (16) defining openings (17) for the formation of resistors, low-dose ionic implantation (18) through the implantation mask to form pairs of regions (19, 20) at the sides of the gate strips (14) and resistive regions (21) through the openings, the formation of an insulating layer (30) on the entire structure thus produced, and anisotropic etching of the insulating layer (30) so as to uncover the areas of the substrate not covered by the polycrystalline silicon mask but leaving a residue (22) of insulating material along the edges of the gate strips (14). To compensate for the removal of a surface layer from the resistive regions due to the anisotropic etching, a second low-dose implantation is carried out without masking of the substrate, with a dose and an energy such as to produce a predetermined resistivity for the resistive regions (21) without altering the resistivities of the source and drain regions of the MOS transistors.

    Abstract translation: 描述的方法提供用于多晶硅包括条带的注入掩模（14）的形成构成MOS晶体管的栅电极的部分和（16） - 定义的开口（17），用于电阻器，低剂量的离子注入的形成（ 18）通过上述注入掩模，以形成区域的对（19，20）在栅极条带（14）和电阻性区域（21）通过开口，在整个结构上的绝缘层（30）的形成。因此侧面 产生，并且在绝缘层（30）的各向异性蚀刻，以露出未包括的多晶硅掩模但留下沿着栅极条带（14）的边缘的绝缘材料的残基（22）的基板的面积。 为了补偿用于去除来自电阻区域的表面层的由于各向异性蚀刻，第二低剂量注入被执行，而不在基板的掩蔽，具有剂量和能量：如以产生预定电阻率的电阻 区域（21），而不改变MOS晶体管的源和漏区的电阻率。

    Method for forming a plurality of parallel floating gate regions by avoiding poly stringers formation
    17.
    发明公开
    Method for forming a plurality of parallel floating gate regions by avoiding poly stringers formation 失效
    制造多个平行的浮栅区域的免费同时避免多晶硅残基的形成的方法

    公开(公告)号：EP0902463A1

    公开(公告)日：1999-03-17

    申请号：EP97830433.5

    申请日：1997-08-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Cassio, Valerio ,  Wurthwein, Arturo

    IPC: H01L21/321 ,  H01L21/8247

    CPC classification number: H01L27/11521 ,  H01L21/32139

    Abstract: A method of manufacturing a plurality of floating gate regions lying parallel on a semiconductor substrate (10), and of inhibiting the formation of residue materiallaterally contiguous to each floating gate region, comprises the following steps: growing a thin oxide layer (13) over the semiconductor substrate (10); depositing a first layer (14) of polysilicon to fully cover the first thin oxide layer; growing and/or depositing an intermediate dielectric layer (15) over the first layer (14) of polysilicon; depositing a second layer (16) of polysilicon to fully cover the intermediate dielectric layer (15). This method further comprises the steps of depositing a final dielectric layer (17) to cover the previously deposited and/or grown layers (13,14,15,16); depositing a layer of resist onto the final dielectric layer, followed by a photolithographing step to define a planar geometry bounding the floating gate regions; and carrying out a first etching to only transfer this planar geometry onto the final dielectric layer (17), thereby producing a mask for a late second etching of the self-aligned type; thoroughly removing the layer of resist; carrying out a second self-aligned etching to spatially define the floating gate regions with a vertical profile.

    Abstract translation: 制造浮在一个半导体衬底（10）位于平行的栅极区域中的多个方法，和残余材料尾盘反弹邻接的各浮栅区的形成，抑制的方法包括以下步骤：生长在一薄的氧化物层（13） 半导体衬底（10）; 沉积多晶硅完全覆盖第一薄氧化物层的第一层（14）; 生长和/或在多晶硅的第一层（14）中间介电层（15）上沉积; 沉积多晶硅的第二层（16）完全覆盖中间介电层（15）。 该方法还包括沉积最终介电层（17），以覆盖先前沉积和/或生长的层（13,14,15,16）的步骤; 沉积抗蚀剂层到最终的介电层，接着是步骤photolithographing以限定平面的几何形状界定浮栅区; 并进行第一蚀刻，以仅传输该平面的几何形状到最终的介电层（17），由此产生的自对准型的后期第二蚀刻的掩模; 彻底除去抗蚀剂的层; 进行第二自对准蚀刻到空间上与垂直轮廓限定在浮置栅极区域。

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