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公开(公告)号：JPH01185038A
公开(公告)日：1989-07-24
申请号：JP827888
申请日：1988-01-20
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To simplify a device by providing an encoding means to read digital signals from plural storing means, respectively, and to encode them through the use of ununiform error correcting code and a decoding means to decode according to the encoding means. CONSTITUTION:The digital signals are stored into respective storing means 3-1-3-8 according to the degrees of distortions to be given to output waveforms when transmission errors are generated, and the ununiform error correcting codes are added to the digital signals stored by the storing means 3-1-3-8. The encoding is executed by using an encoding means 5 for digital signals to which the ununiform error correcting codes are added. The encoded digital signals are decoded by a decoding means 7 corresponding to the encoding means 5. The encoding means 5 and decoding means 7 are provided in order to commonly encode and decode respective storing means 3-1-3-8. Thus, the device can be simplified, and a construction can be made comparatively simple.
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公开(公告)号：JPS6482714A
公开(公告)日：1989-03-28
申请号：JP23884087
申请日：1987-09-25
Applicant: TOSHIBA CORP
Inventor： NAKAMURA MAKOTO
IPC: H04B7/15
Abstract: PURPOSE:To reduce the collision of different-length burst signals when they are present by generating a timing signal for a transmission start position and performing transmission while synchronizing the burst signals with the timing signal. CONSTITUTION:The burst signals have >=2 kinds of length, a center station sets the timing intervals of transmission start positions according to the length of the shortest burst signal, and terminal stations 10a-10p send out the burst signals in synchronism with the timing of the transmission start positions. Namely, when the burst signals are sent out, they are sent out while only the transmission position positions are synchronized, and the timing intervals of the burst signals are set by using only the shortest burst signal. Further, the transmission start positions of the burst signals are set at determined intervals, so even when handled packet length is different, the transmission start timing intervals are only determined to eliminate the need for control under which the burst signals are sent out by selecting the length matching with the transmission start timing intervals.
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公开(公告)号：JPS62208718A
公开(公告)日：1987-09-14
申请号：JP21013285
申请日：1985-09-25
Applicant: TOSHIBA CORP
Inventor： NAKAMURA MAKOTO , SUZUKI HIDEO , KUROKI TOSHIHIKO
IPC: H03M7/50
Abstract: PURPOSE:To decrease number of externally mounted components to an LSI for miniaturization and to prevent the distortion of reproduced sound by outputting a linear PCM signal obtained by the 1st means through an external terminal externally and supplying the linear PCM signal externally from other external terminal and leading the linear PCM signal to the 2nd means. CONSTITUTION:An ADPCM signal is released of coding by an ADPCM decoding circuit 104 and becomes a linear PCM signal. then the signal is outputted at the outside of an LSI 100 via a terminal 108 or fetched from the outside of the LSI 100 via a terminal 110. A switch circuit 106 selects an output signal of the ADPCM decoding circuit 104 and a signal from the terminal 110 and gives the result as an output in response to a signal supplied from an external control terminal 112. The output signal of the switch circuit 106 is a linear PCM signal and converted into a mu-law PCM signal at a PCM signal converter 114. The signal becomes an excellent sound signal without analog distortion by a mu-law PCM CODEC 118.
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公开(公告)号：JPS6277724A
公开(公告)日：1987-04-09
申请号：JP21833385
申请日：1985-09-30
Applicant: TOSHIBA CORP
Inventor： KISHINO AYANORI , NAKAMURA MAKOTO
Abstract: PURPOSE:To repair a line without interrupting an operating line by collecting the information of communication line assignment of an earth station just before an error takes place and resetting a communication line with the earth station when the system is restored into a normal operation after the error takes place. CONSTITUTION:Station control processors (SCP) 1-1-1-n have managing tables 2-1-2-n and store the line operating state of their own station, the operating frequency, or the information such as the operating time slot or inter-station connection state respectively. When a network control processor (NCP) 3 restores to the normal operation, a line request inhibition command to each SCP, each SCP reads the information just before the occurrence of an error from the managing table of its own station and sends it to the NCP 3. Then the NCP 3 reedits the management table 5 and sends the permission signal of a new line setting request without interrupting the operating line.
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公开(公告)号：JPS61202541A
公开(公告)日：1986-09-08
申请号：JP4391485
申请日：1985-03-06
Applicant: TOSHIBA CORP
Inventor： UNO SHINTARO , NAKAMURA MAKOTO
Abstract: PURPOSE:To decrease collision probability of data with priority by specifying a assigned channel in response to the priority provided to the data from each communication station and setting many channel numbers possible for assignment as the priority is higher. CONSTITUTION:Data from earth stations 101-10n are assigned to any of plural time slots A line is provided with time slots N1, N2, N3 arranged in time series in succession to a reference burst D0 from a line control station 30. The data from each earth station are classified into groups A, B, C in the higher order of communication priority. Then the date belonging to the group A is assigned to any of the time slots N1, N2, N3, the data belonging to the group B is assigned to any of the N2, N3 and the data belonging to the group C is assigned only to the N3.
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Patent Agency Ranking
公开(公告)号：JPS58215822A
公开(公告)日：1983-12-15
申请号：JP9951482
申请日：1982-06-10
Applicant: Toshiba Corp
Inventor： SUGIYAMA FUMIO , NAKAMURA MAKOTO
CPC classification number: H03M7/3044
Abstract: PURPOSE:To simplify the constitution of a titled device, by constituting a predictive circuit for the encoder encoding a difference signal between an estimated instantaneous value and a present instantaneous value of a lattice type digital filter and an adder summing its outputs, for performing stable predictive processing to a voice signal. CONSTITUTION:A voice signal analyzing circuit obtains a characteristic parameter signal of a voice signal from the past sampling value of the voice signal and inputs the parameter signal to the predictive circuit to obtain the estimated predictive value to the voice signal. This predictive circuit is constituted of the lattice type digital filter 5c and the adder 5d obtaining the total sum of the tap outputs of the filter 5c. A decoded difference signal deltan'' inputted by the filter 5c is transmitted sequentially via adders 21-1-21-8, and the output is transmitted through delay circuits 22-8-22-1 and adders 23-8-23-2 alternately. The output of the adders 21-2-21-8 is applied to multipliers 24-2-24-8 to multiply the autocorrelation coefficient, which is applied to the adders 21-8-21-1 for making the predictive processing stable.
Abstract translation: 目的：为了简化标题设备的结构，通过构成编码编码码格式数字滤波器的估计瞬时值和当前瞬时值之间的差分信号的编码器的预测电路以及对其输出求和的加法器，用于执行稳定预测 处理到语音信号。 构成：语音信号分析电路根据语音信号的过去采样值获得语音信号的特征参数信号，并将参数信号输入到预测电路，以获得对语音信号的估计预测值。 该预测电路由格子型数字滤波器5c和加法器5d构成，得到滤波器5c的抽头输出的总和。 通过加法器21-1-21-8依次发送由滤波器5c输入的解码差分信号deltan'，并且输出通过延迟电路22-8-22-1和加法器23-8-23-2交替地发送 。 加法器21-2-21-8的输出被施加到乘法器24-2-24-8以乘以将自相关系数乘以加法器21-8-21-1以使预测处理稳定。
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公开(公告)号：JPH06311053A
公开(公告)日：1994-11-04
申请号：JP9933693
申请日：1993-04-26
Applicant: TOSHIBA CORP
Inventor： NAKAMURA MAKOTO
Abstract: PURPOSE:To decode data with high reliability in the communication system or the recording system. CONSTITUTION:An error correction coder 101 is provided with convolution coders 12, 13 applying error correction coding to a convolution coding signal in which 1st and 2nd information series are not compressed, a signal conversion circuit 14 using output signals A2, B2 being parts of the output signals from the convolution coders 12, 13 to apply signal conversion possible for reversible arithmetic operation to generate a convolution coding signal C to be compressed, and an output device applying convolution processing to output signals A1, B1 other than output signals A2, B2 from the convolution coder and to an output signal C to provide a convolution coding signal to output it, and an error correction decoder 102 has delay circuits 22, 23, 24 synchronizing the signals and Viterbi decoders 34, 44 or the like decoding information signals Y'', X''.
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公开(公告)号：JPH0344217A
公开(公告)日：1991-02-26
申请号：JP18077589
申请日：1989-07-12
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
IPC: H03M13/00
Abstract: PURPOSE:To attain the decoding of an error correction code with only the addition of a simple circuit by providing a threshold level decision means deciding whether or not the weight of a residue series calculated from a reception signal series is less than a threshold level. CONSTITUTION:The device is provided with a signal input means 101 inputting a reception signal series, a signal storage means 102 storing the reception signal series inputted from the signal input means 101, a residue calculation means 103 calculating a residue series from the reception signal series, and a threshold level decision means 104 deciding whether or not the weight of the residue series is the threshold level or below. Moreover, the device is provided with a pattern detection means 105 detecting whether or not the residue series calculated by the residue calculation means 103 is coincident with a preset prescribed pattern, an error correction means 106 correcting an error of a stored reception signal series by the signal storage means 102 based on the result of detection and a signal output means 107. Thus, the decoding of the error correction code is attained by having only to add a simple circuit.
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公开(公告)号：JPH02311034A
公开(公告)日：1990-12-26
申请号：JP13162189
申请日：1989-05-26
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To increase the coding rate of an error correction circuit, to shorten the decoding delay time and to increase the degree of freedom of coding by using an error correction circuit by a BCH code as a block code in the inside of a differential logic circuit. CONSTITUTION:A digital signal series is inputted from an input terminal 101 at a transmission side and fed to a differential logic coding circuit 102. The circuit applies additive operation to the series and the series obtained as the result is fed to a BCH coding circuit 103. The circuit 103 applies coding with binary BCH code and the result is fed to a BPSK modulator 104. However, the generation polynomial of the BCH code does not have 1 as its root. The modulator 104 outputs a BPSK modulation signal to a channel S and transmitted to a reception side BPSK demodulator 105. Then decoding and differential operation are applied via the BCH decoding circuit 106 and a differential logic decoding circuit 107 and the result is outputted from an output terminal 108. Thus, the coding rate of the error correction circuit is increased to increase the degree of freedom of coding and the decoding delay time is shortened.
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公开(公告)号：JPH02303221A
公开(公告)日：1990-12-17
申请号：JP12361489
申请日：1989-05-17
Applicant: TOSHIBA CORP
Inventor： MORII MASAKATSU , KASAHARA MASAO , KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To quicken the decoding processing by varying a series of decoding procedures obtaining an error location polynomial and an error numeral polynomial from a residue polynomial in various kinds of ways. CONSTITUTION:A reception symbol R(X) is inputted from an input terminal 1 and supplied to a residue calculation circuit 2 and a storage circuit 3. A fundamental equation arithmetic circuit 4 receives a residue obtained from the residue calculation circuit 2 to obtain coefficients of two polynomials W(X), N(X). The coefficient of the equation W(X) calculated by the fundamental equation arithmetic circuit 4 is fed to an error location calculation circuit 5. When a reed Solomon code is generated by a generation polynomial, number of data stored in a storage circuit 10 is decreased. An error correction circuit 7 corrects an error of reception series to given an output to an output terminal 8.
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