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    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE
    11.
    发明申请
    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210082810A1

    公开(公告)日：2021-03-18

    申请号：US17095744

    申请日：2020-11-12

    Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

    Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Tao-Chih Chang ,  Yu-Min Lin ,  Sheng-Tsai Wu

    IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L25/04

    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

    Package carrier structure having integrated circuit design and manufacturing method thereof
    12.
    发明授权
    Package carrier structure having integrated circuit design and manufacturing method thereof 有权

    公开(公告)号：US10937723B2

    公开(公告)日：2021-03-02

    申请号：US16028440

    申请日：2018-07-06

    Applicant: Unimicron Technology Corp.

    Inventor： Yu-Chung Hsieh ,  Chun-Hsien Chien ,  Yu-Hua Chen

    IPC: H01L23/498 ,  H01L49/02 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40 ,  H01L25/16

    Abstract: A package carrier structure includes an insulating substrate, a first wiring layer, a second wiring layer, at least one conductive via, a plurality of first and second conductive pads, a first insulating layer, a plurality of first and second conductive structures, and an encapsulated layer. The first and second wiring layers are disposed on the upper and lower surfaces of the insulating substrate respectively. The conductive via penetrates through the insulating substrate and electrically connected to the first and second wiring layers. The first and second conductive pads are disposed on the upper surface and electrically connected to the first wiring layer. The first insulating layer is disposed on the upper surface and exposing the first and second conductive pads. The first and second conductive structures are disposed on the first and second conductive pads respectively. The lower surface of the insulating substrate is covered by the encapsulation layer.

    Package substrate structure and bonding method thereof
    13.
    发明授权
    Package substrate structure and bonding method thereof 有权

    公开(公告)号：US10658282B2

    公开(公告)日：2020-05-19

    申请号：US16167540

    申请日：2018-10-23

    Applicant: Unimicron Technology Corp.

    Inventor： Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen ,  Tzyy-Jang Tseng

    IPC: H01L23/498

    Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.

    Package carrier and manufacturing method thereof
    16.
    发明授权
    Package carrier and manufacturing method thereof 有权

    公开(公告)号：US11139234B1

    公开(公告)日：2021-10-05

    申请号：US16942743

    申请日：2020-07-29

    Applicant: Unimicron Technology Corp.

    Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Yu-Hua Chen

    IPC: H05K1/18 ,  H01L23/498 ,  H01L21/48

    Abstract: A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.

    CIRCUIT BOARD ELEMENT AND MANUFACTURING METHOD THEREOF
    17.
    发明申请
    CIRCUIT BOARD ELEMENT AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210193608A1

    公开(公告)日：2021-06-24

    申请号：US17195649

    申请日：2021-03-09

    Applicant: Unimicron Technology Corp.

    Inventor： Yu-Chung Hsieh ,  Chun-Hsien Chien ,  Yu-Hua Chen

    IPC: H01L23/00 ,  H01L21/768 ,  H01L21/027 ,  H05K3/00

    Abstract: A manufacturing method of a circuit board element including the following steps is provided: placing a circuit substrate on a carrier, wherein the circuit substrate includes an insulating layer and a circuit layer disposed thereon, a protective layer disposed on the circuit layer and having a plurality of openings exposing thereof, and a plurality of solder balls disposed on the protective layer and embedded in the openings; forming a trench penetrating the circuit substrate to expose the carrier; forming a photoresist material layer to cover the circuit substrate and filling the spaces between each of the solder balls and the protective layer and is filling in the trench to cover the carrier; curing a portion of the photoresist material layer filled in the spaces to form a dielectric layer; removing a portion of the photoresist material layer filled in the trench to expose the carrier; and removing the carrier.

    Package structure and bonding method thereof
    18.
    发明授权
    Package structure and bonding method thereof 有权

    公开(公告)号：US10756050B2

    公开(公告)日：2020-08-25

    申请号：US16152424

    申请日：2018-10-05

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen

    IPC: H01L29/40 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

    Abstract: A package structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The pads are disposed on the first substrate, and fill the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package structure is also provided.

    LIGHT-EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF
    19.
    发明申请
    LIGHT-EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200161518A1

    公开(公告)日：2020-05-21

    申请号：US16281108

    申请日：2019-02-21

    Applicant: Unimicron Technology Corp.

    Inventor： Yi-Cheng Lin ,  Yu-Hua Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Cheng-Hui Wu

    IPC: H01L33/62 ,  H01L33/52 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31

    Abstract: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.

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