公开(公告)号：EP2298448A2

公开(公告)日：2011-03-23

申请号：EP10181157.8

申请日：2003-09-24

Applicant: California Institute of Technology

Inventor： Maerkl, Sebastian J ,  Thorsen, Todd A ,  Xiaoyan, Bao ,  Quake, Stephen R ,  Studer, Vincent

IPC: B01L3/00 ,  B81B1/00 ,  F15C5/00 ,  B81B3/00

CPC classification number: C12Q1/28 ,  B01L3/5025 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0861 ,  B01L2300/0887 ,  B01L2400/0481 ,  B01L2400/0655 ,  B81B2201/0214 ,  B81B2201/054 ,  B81B2201/07 ,  B81C1/00119 ,  F15C5/00 ,  F16K11/20 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0059 ,  F16K2099/0074 ,  F16K2099/0076 ,  F16K2099/0078 ,  F16K2099/008 ,  F16K2099/0084 ,  F16K2099/0094 ,  Y10T137/0318 ,  Y10T137/0329 ,  Y10T137/2224 ,  Y10T137/85938 ,  Y10T137/87249

Abstract: High-density microfluidic chips contain plumbing networks with thousands of micromechanical valves and hundreds of individually addressable chambers. These fluidic devices are analogous to electronic integrated circuits fabricated using large scale integration (LSI). A component of these networks is the fluidic multiplexor, which is a combinatorial array of binary valve patterns that exponentially increases the processing power of a network by allowing complex fluid manipulations with a minimal number of inputs. These integrated microfluidic networks can be used to construct a variety of highly complex microfluidic devices, for example the microfluidic analog of a comparator array, and a microfluidic memory storage device resembling electronic random access memories.

Abstract translation: 高密度微流控芯片包含具有数千个微机械阀门和数百个可单独寻址的腔室的管道网络。 这些流体装置类似于使用大规模集成（LSI）制造的电子集成电路。 这些网络的一个组成部分是流体多路复用器，它是二进制阀模式的组合阵列，通过允许使用最少数量的输入的复杂流体操纵来指数地增加网络的处理能力。 这些集成微流体网络可用于构建各种高度复杂的微流体装置，例如用于隔离异质样品的元件的装置。

公开(公告)号：EP1551753A2

公开(公告)日：2005-07-13

申请号：EP03774496.8

申请日：2003-09-24

Applicant: California Institute of Technology

Inventor： MAERKL, Sebastian, J. ,  THORSEN, Todd, A. ,  BAO, Xiaoyan ,  QUAKE, Stephen, R. ,  STUDER, Vincent

IPC: B81B1/00

CPC classification number: C12Q1/28 ,  B01L3/5025 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0861 ,  B01L2300/0887 ,  B01L2400/0481 ,  B01L2400/0655 ,  B81B2201/0214 ,  B81B2201/054 ,  B81B2201/07 ,  B81C1/00119 ,  F15C5/00 ,  F16K11/20 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0059 ,  F16K2099/0074 ,  F16K2099/0076 ,  F16K2099/0078 ,  F16K2099/008 ,  F16K2099/0084 ,  F16K2099/0094 ,  Y10T137/0318 ,  Y10T137/0329 ,  Y10T137/2224 ,  Y10T137/85938 ,  Y10T137/87249

Abstract: High-density microfluidic chips contain plumbing networks with thousands of micromechanical valves and hundreds of individually addressable chambers. These fluidic devices are analogous to electronic integrated circuits fabricated using large scale integration (LSI). A component of these networks is the fluidic multiplexor, which is a combinatorial array of binary valve patterns that exponentially increases the processing power of a network by allowing complex fluid manipulations with a minimal number of inputs. These integrated microfluidic networks can be used to construct a variety of highly complex microfluidic devices, for example the microfluidic analog of a comparator array, and a microfluidic memory storage device resembling electronic random access memories.

Abstract translation: 高密度微流控芯片包含具有数千个微机械阀门和数百个可单独寻址的腔室的管道网络。 这些流体装置类似于使用大规模集成（LSI）制造的电子集成电路。 这些网络的一个组成部分是流体多路复用器，它是二进制阀模式的组合阵列，通过允许使用最少数量的输入的复杂流体操纵来指数地增加网络的处理能力。 这些集成的微流体网络可用于构建各种高度复杂的微流体装置，例如比较器阵列的微流体模拟装置和类似于电子随机存取存储器的微流体存储器存储装置。

公开(公告)号：JP3998266B2

公开(公告)日：2007-10-24

申请号：JP50691697

申请日：1996-07-19

Applicant: カーネギー メロン ユニバーシティ

Inventor： カーレイ，エル，リチャード ,  サンサナム，スレシュ ,  フェッダー，ゲイリー，ケイ． ,  リード，マイケル，エル．

IPC: G01B21/30 ,  G11B9/14 ,  B62D57/00 ,  B81B3/00 ,  B81B5/00 ,  B81B7/02 ,  B81C3/00 ,  G01N13/10 ,  G01N37/00 ,  G11B5/00 ,  G11B9/00 ,  G11B9/04 ,  H02N1/00

CPC classification number: H02N1/006 ,  B81B2201/07 ,  B81B2201/12 ,  B81B2203/0361 ,  B81C1/0015 ,  B81C2201/0109 ,  B81C2201/0132 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1418 ,  G11B9/1445 ,  G11B2005/0002 ,  Y10S977/861 ,  Y10S977/881 ,  Y10S977/888 ,  Y10S977/89

公开(公告)号：US20230143421A1

公开(公告)日：2023-05-11

申请号：US18148684

申请日：2022-12-30

Applicant: Micron Technology, Inc .

Inventor： Tomoharu Tanaka ,  Yoshiaki Fukuzumi

IPC: G11C11/4097 ,  H10B41/20 ,  H10B41/41 ,  H10B43/40 ,  G11C11/4091 ,  B81B7/00 ,  H10B43/20

CPC classification number: G11C11/4097 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11573 ,  G11C11/4091 ,  B81B7/008 ,  H01L27/11578 ,  B81B2201/07

Abstract: A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US09755041B2

公开(公告)日：2017-09-05

申请号：US14701502

申请日：2015-04-30

Applicant: Purdue Research Foundation

Inventor： Muhammad Ashraful Alam ,  Muhammad Masuduzzaman ,  Ankit Jain

IPC: G01L9/00 ,  H01L21/00 ,  H01L29/51 ,  H01L29/78 ,  H01L27/11502 ,  H01L27/11585 ,  B81B7/02 ,  H01G4/38 ,  H01L27/08 ,  H01G5/16 ,  H01G5/40 ,  H01G7/06 ,  H01L49/02

CPC classification number: H01L29/515 ,  B81B7/02 ,  B81B2201/014 ,  B81B2201/016 ,  B81B2201/07 ,  H01G4/38 ,  H01G5/16 ,  H01G5/40 ,  H01G7/06 ,  H01L27/0805 ,  H01L27/11502 ,  H01L27/11585 ,  H01L29/516 ,  H01L29/7842

Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.

公开(公告)号：US09714443B2

公开(公告)日：2017-07-25

申请号：US13679328

申请日：2012-11-16

Applicant: California Institute of Technology

Inventor： Sebastian J. Maerkl ,  Todd A. Thorsen ,  Xiaoyan Bao ,  Stephen R. Quake ,  Vincent Studer

IPC: B81B3/00 ,  B81B7/00 ,  B01L3/00 ,  C12Q1/28 ,  B81C1/00 ,  F15C5/00 ,  F16K99/00

CPC classification number: C12Q1/28 ,  B01L3/5025 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0861 ,  B01L2300/0887 ,  B01L2400/0481 ,  B01L2400/0655 ,  B81B2201/0214 ,  B81B2201/054 ,  B81B2201/07 ,  B81C1/00119 ,  F15C5/00 ,  F16K11/20 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0059 ,  F16K2099/0074 ,  F16K2099/0076 ,  F16K2099/0078 ,  F16K2099/008 ,  F16K2099/0084 ,  F16K2099/0094 ,  Y10T137/0318 ,  Y10T137/0329 ,  Y10T137/2224 ,  Y10T137/85938 ,  Y10T137/87249

Abstract: High-density microfluidic chips contain plumbing networks with thousands of micromechanical valves and hundreds of individually addressable chambers. These fluidic devices are analogous to electronic integrated circuits fabricated using large scale integration (LSI). A component of these networks is the fluidic multiplexor, which is a combinatorial array of binary valve patterns that exponentially increases the processing power of a network by allowing complex fluid manipulations with a minimal number of inputs. These integrated microfluidic networks can be used to construct a variety of highly complex microfluidic devices, for example the microfluidic analog of a comparator array, and a microfluidic memory storage device resembling electronic random access memories.

公开(公告)号：US20160332871A1

公开(公告)日：2016-11-17

申请号：US15220267

申请日：2016-07-26

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Giuseppe Barillaro ,  Alessandro Diligenti ,  Caterina Riva ,  Roberto Campedelli ,  Stefano Losa

IPC: B81C1/00

CPC classification number: B81C1/00539 ,  B81B2201/038 ,  B81B2201/07 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/019 ,  B81C1/00595 ,  B81C2201/0136 ,  B81C2203/0714 ,  H01L27/10

Abstract: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of conductivity and a top surface; forming a first interaction region having a second type of conductivity, opposite to the first type of conductivity, in a surface portion of the substrate in the proximity of the top surface; and carrying out an electrochemical etch of the substrate starting from the top surface, the etching being selective with respect to the second type of conductivity, so as to remove the surface portion of the substrate and separate the first interaction region from the substrate, thus forming the supporting element.

Abstract translation: 一种用于制造用于存储介质的微机电类型的相互作用系统的方法，具有支撑元件的相互作用系统和由支撑元件承载的相互作用元件，其设想是提供具有基板的半导体材料晶片，其具有 第一类导电性和顶面; 在所述顶表面附近的所述衬底的表面部分中形成具有与所述第一类型导电性相反的第二导电类型的第一相互作用区域; 并且从顶表面开始进行基板的电化学蚀刻，蚀刻相对于第二类型的导电性是选择性的，以便去除基板的表面部分并将第一相互作用区域与基板分离，从而形成 支撑元件。

公开(公告)号：US20090272172A1

公开(公告)日：2009-11-05

申请号：US12431213

申请日：2009-04-28

Applicant: Yeau-Ren Jeng ,  Chung-Ming Tan

Inventor： Yeau-Ren Jeng ,  Chung-Ming Tan

IPC: B21D31/00

CPC classification number: B81C1/00031 ,  B81B2201/07 ,  B82Y10/00 ,  G11B9/149 ,  Y10T29/49147 ,  Y10T29/49151 ,  Y10T29/49155

Abstract: The present invention discloses a method for generating nano patterns upon material surfaces. The method for generating nano patterns upon material surfaces comprises the following steps: providing a thin film capable of controlling lattice directions, applying a nanoindentation action to the thin film to generate an indentation at a specific position on the thin film. At least one hillock is then generated in a specific direction to generate a pattern and to be applied to a data storage system.

Abstract translation: 本发明公开了一种在材料表面上产生纳米图案的方法。 在材料表面上产生纳米图案的方法包括以下步骤：提供能够控制晶格方向的薄膜，对薄膜施加纳米压痕作用以在薄膜上的特定位置产生凹陷。 然后在特定方向上产生至少一个小丘以产生模式并应用于数据存储系统。

公开(公告)号：US20080029169A1

公开(公告)日：2008-02-07

申请号：US11463241

申请日：2006-08-08

Applicant: Sebastian J. Maerkl ,  Todd A. Thorsen ,  Xiaoyan Bao ,  Stephen R. Quake ,  Vincent Studer

Inventor： Sebastian J. Maerkl ,  Todd A. Thorsen ,  Xiaoyan Bao ,  Stephen R. Quake ,  Vincent Studer

IPC: F16K11/20

CPC classification number: C12Q1/28 ,  B01L3/5025 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0861 ,  B01L2300/0887 ,  B01L2400/0481 ,  B01L2400/0655 ,  B81B2201/0214 ,  B81B2201/054 ,  B81B2201/07 ,  B81C1/00119 ,  F15C5/00 ,  F16K11/20 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0059 ,  F16K2099/0074 ,  F16K2099/0076 ,  F16K2099/0078 ,  F16K2099/008 ,  F16K2099/0084 ,  F16K2099/0094 ,  Y10T137/0318 ,  Y10T137/0329 ,  Y10T137/2224 ,  Y10T137/85938 ,  Y10T137/87249

Abstract: High-density microfluidic chips contain plumbing networks with thousands of micromechanical valves and hundreds of individually addressable chambers. These fluidic devices are analogous to electronic integrated circuits fabricated using large scale integration (LSI). A component of these networks is the fluidic multiplexor, which is a combinatorial array of binary valve patterns that exponentially increases the processing power of a network by allowing complex fluid manipulations with a minimal number of inputs. These integrated microfluidic networks can be used to construct a variety of highly complex microfluidic devices, for example the microfluidic analog of a comparator array, and a microfluidic memory storage device resembling electronic random access memories.

Abstract translation: 高密度微流控芯片包含具有数千个微机械阀门和数百个单独可寻址腔室的管道网络。 这些流体装置类似于使用大规模集成（LSI）制造的电子集成电路。 这些网络的一个组件是流体多路复用器，它是二进制阀模式的组合阵列，通过允许使用最少数量的输入的复杂流体操纵来指数地增加网络的处理能力。 这些集成的微流体网络可用于构建各种高度复杂的微流体装置，例如比较器阵列的微流体模拟装置和类似于电子随机存取存储器的微流体存储器存储装置。

公开(公告)号：WO2010098633A3

公开(公告)日：2010-12-09

申请号：PCT/KR2010001255

申请日：2010-02-26

Applicant: UNIV SUNGKYUNKWAN FOUND ,  KIM YONG TAE ,  LEE WOO HWANG ,  KIM DOO SHIK ,  LEE HYUN JU ,  KWON YOUNG UK

Inventor： KIM YONG TAE ,  LEE WOO HWANG ,  KIM DOO SHIK ,  LEE HYUN JU ,  KWON YOUNG UK

IPC: B82B1/00 ,  B82B3/00

CPC classification number: B81C1/00031 ,  B81B2201/07 ,  B81B2207/056 ,  B82B3/00 ,  B82Y25/00 ,  B82Y30/00 ,  B82Y40/00 ,  G11B5/855 ,  G11B5/858 ,  H01F1/0063 ,  H01F1/0081 ,  H01F1/009 ,  H01F41/34

Abstract: The present invention relates to a laminated nanostructure including magnetic nanoparticles having a perpendicular magnetic anisotropy, to a method for producing same, and to a magnetic storage medium using same. More particularly, the present invention relates to a laminated nanostructure which is produced using a porous thin film as a template, and by depositing magnetic nanoparticles in the pores of the thin film through an electrodeposition process. As a result, the gaps between nanoparticles are uniform, the sizes of nanoparticles are small, and nanoparticles are free from a polarity interaction therebetween, thus enabling each of the nanoparticles to have its own polarity, and to achieve perpendicular magnetic properties.

Abstract translation: 本发明涉及包括具有垂直磁各向异性的磁性纳米粒子的层压纳米结构体及其制造方法以及使用其的磁性存储介质。 更具体地，本发明涉及使用多孔薄膜作为模板制备的层压纳米结构体，并且通过电沉积方法将磁性纳米颗粒沉积在薄膜的孔中。 结果，纳米颗粒之间的间隙是均匀的，纳米颗粒的尺寸小，并且纳米颗粒之间没有极性相互作用，从而使得每个纳米颗粒具有其自己的极性，并实现垂直磁性。