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    Semiconductor device and manufacturing method of the same
    12.
    发明专利
    Semiconductor device and manufacturing method of the same 审中-公开
    半导体器件及其制造方法

    公开(公告)号：JP2012142641A

    公开(公告)日：2012-07-26

    申请号：JP2012104835

    申请日：2012-05-01

    Applicant: Fujikura Ltd ,  株式会社フジクラ

    Inventor： YAMAMOTO SATOSHI ,  HASHIMOTO HIROKAZU

    IPC: H01L23/02

    CPC classification number: B81C1/00317 ,  B81C2201/0104 ,  B81C2201/0108 ,  B81C2201/0125 ,  B81C2203/0118 ,  B81C2203/0145 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can manufacture in a simpler process a semiconductor device capable of inhibiting unevenness and cracks after grinding caused by presence of existence and non-existence of a cavity and contributing to downsizing of devices and electronic equipment on which the devices are mounted.SOLUTION: A semiconductor device manufacturing method comprises in order: a bonding step of bonding a first substrate having light permeability with a second substrate provided with a functional element on one face such that the functional element faces the first substrate; a thinning process of thinning at least one of the first substrate and the second substrate; and a through hole forming step of forming a cavity and a through hole communicating with the cavity on at least a part of a bonded part of the first substrate and the second substrate.

    Abstract translation: 解决问题的方案：提供一种半导体器件制造方法，其可以以更简单的方法制造能够抑制由于存在和不存在空腔而导致的研磨后的不均匀性和裂纹的半导体器件，并有助于小型化 设备和电子设备。 解决方案：半导体器件制造方法包括以下步骤：将具有透光性的第一衬底与设置有功能元件的第二衬底接合在一个面上以使得功能元件面向第一衬底的接合步骤; 减薄所述第一基板和所述第二基板中的至少一个的薄化处理; 以及通孔形成步骤，在所述第一基板和所述第二基板的接合部的至少一部分上形成与所述空腔连通的空腔和通孔。 版权所有（C）2012，JPO＆INPIT

    FABRICATING STRUCTURES USING CHEMO-MECHANICAL POLISHING AND CHEMICALLY-SELECTIVE ENDPOINT DETECTION
    13.
    发明申请
    FABRICATING STRUCTURES USING CHEMO-MECHANICAL POLISHING AND CHEMICALLY-SELECTIVE ENDPOINT DETECTION 审中-公开
    使用化学机械抛光和化学选择性端点检测的织造结构

    公开(公告)号：WO03005421A3

    公开(公告)日：2003-08-28

    申请号：PCT/US0220453

    申请日：2002-06-26

    Applicant: UNIV CALIFORNIA

    Inventor： PETERSON JEFFREY ,  HUNT CHARLES

    IPC: B24B37/04 ,  B81C1/00 ,  H01L21/306 ,  B81B1/00

    CPC classification number: B81C1/00611 ,  B24B37/013 ,  B24B37/042 ,  B81C2201/0104 ,  B81C2201/0123 ,  H01L21/30604 ,  H01L21/30608

    Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain. The system then forms a third layer composed of a third material over the first layer and the remaining portions of the second layer, and performs a second etching operation using a selective etchant to remove the remaining portions of the second layer, thereby creating voids between the first layer and the third layer.

    Abstract translation: 本发明的一个实施方案提供了一种使用选择性蚀刻在硅衬底上形成结构的方法。 该处理开始于接收硅衬底，第一层由第一材料组成，第一层包括由第一蚀刻操作产生的空隙。 然后，该过程在第一层上形成由第二材料构成的第二层，使得第二层填充由第一蚀刻操作产生的第一层中的空隙的部分。 接下来，该过程在第二层上进行到第一层的化学机械抛光操作，使得仅在由第一蚀刻操作产生的空隙内的第二层的剩余部分保留。 然后，该系统在第一层和第二层的其余部分上形成由第三材料组成的第三层，并且使用选择性蚀刻剂进行第二蚀刻操作以去除第二层的剩余部分，从而在第二层之间产生空隙 第一层和第三层。

    FABRICATING STRUCTURES USING CHEMO-MECHANICAL POLISHING AND CHEMICALLY-SELECTIVE ENDPOINT DETECTION
    14.
    发明申请
    FABRICATING STRUCTURES USING CHEMO-MECHANICAL POLISHING AND CHEMICALLY-SELECTIVE ENDPOINT DETECTION 审中-公开
    化学机械抛光和化学选择性终点检测法制备结构

    公开(公告)号：WO2003005421A2

    公开(公告)日：2003-01-16

    申请号：PCT/US2002/020453

    申请日：2002-06-26

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    Inventor： PETERSON, Jeffrey ,  HUNT, Charles

    IPC: H01L21/00

    CPC classification number: B81C1/00611 ,  B24B37/013 ,  B24B37/042 ,  B81C2201/0104 ,  B81C2201/0123 ,  H01L21/30604 ,  H01L21/30608

    Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain. The system then forms a third layer composed of a third material over the first layer and the remaining portions of the second layer, and performs a second etching operation using a selective etchant to remove the remaining portions of the second layer, thereby creating voids between the first layer and the third layer.

    Abstract translation: 本发明的一个实施例提供了一种使用选择性蚀刻在硅衬底上形成结构的工艺。 该过程开始于接收具有由第一材料构成的第一层的硅衬底，该第一材料包括由第一蚀刻操作产生的空隙。 然后该过程在第一层上形成由第二材料构成的第二层，使得第二层填充由第一蚀刻操作产生的第一层中的空隙的部分。 接下来，该过程在第二层上执行化学机械抛光操作直至第一层，使得仅留下由第一蚀刻操作产生的空隙内的第二层的剩余部分。 该系统然后在第一层和第二层的其余部分之上形成由第三材料构成的第三层，并且使用选择性蚀刻剂执行第二蚀刻操作以去除第二层的剩余部分，从而在第二层之间产生空隙 第一层和第三层。

    THICK SANDWICH WAFER FOR MEMS FABRICATION
    15.
    发明申请
    THICK SANDWICH WAFER FOR MEMS FABRICATION 审中-公开
    用于MEMS制造的厚砂光纤

    公开(公告)号：WO2002090243A2

    公开(公告)日：2002-11-14

    申请号：PCT/GB2002/002009

    申请日：2002-05-02

    Applicant: ALCATEL OPTRONICS UK LIMITED ,  BLAIRE, Paul ,  PODLECKI, Jean

    Inventor： BLAIRE, Paul ,  PODLECKI, Jean

    IPC: B81B3/00

    CPC classification number: B81C1/00142 ,  B81B3/004 ,  B81B2201/042 ,  B81C2201/0104 ,  B81C2201/0109 ,  B81C2201/019 ,  G02B26/0841

    Abstract: An improved method of manufacturing MEMS devices having relatively large components, such as large diameter micro mirrors, which require to be tilted at an angle to the wafer substrate, or displaced generally vertically, is described. In the described embodiment an SOI wafer having a sacrificial oxide layer at least 20 μm thick is formed. This provides sufficient space between the wafer substrate and a component formed in the upper silicon layer to allow a relatively large component to be tilted or displaced by a desired amount relative to the wafer substrate, The SOI wafer may be formed by bonding two separate SOI wafers together, A MEM device formed according to the method is also claimed.

    Abstract translation: 描述了一种改进的制造具有相对大的部件的MEMS器件的方法，例如大直径微镜，其需要与晶片衬底成一定角度倾斜，或大致垂直移位。 在所描述的实施例中，形成具有至少20μm厚的牺牲氧化物层的SOI晶片。 这在晶片衬底和形成在上硅层中的部件之间提供了足够的空间，以允许相对较大的部件相对于晶片衬底倾斜或移位所需的量。SOI晶片可以通过将两个分离的SOI晶片 一起，还要求保护根据该方法形成的MEM装置。

    METHOD OF FORMING NON-PLANAR MEMBRANES USING CMP
    19.
    发明公开
    METHOD OF FORMING NON-PLANAR MEMBRANES USING CMP 有权
    工艺用于生产具有化学机械抛光非平面膜

    公开(公告)号：EP2697156A1

    公开(公告)日：2014-02-19

    申请号：EP12716951.4

    申请日：2012-04-13

    Applicant: Robert Bosch GmbH

    Inventor： GRAHAM, Andrew, B. ,  YAMA, Gary ,  O'BRIEN, Gary

    IPC: B81C1/00

    CPC classification number: B81C1/00103 ,  B81B2203/0376 ,  B81C2201/0104

    Abstract: A method of shaping a substrate in one embodiment includes providing a first support layer, providing a first shaping pattern on the first support layer, providing a substrate on the first shaping pattern, performing a first chemical mechanical polishing (CMP) process on the substrate positioned on the first shaping pattern, and removing the once polished substrate from the first shaping pattern.

    PROCESS FOR FILLING ETCHED HOLES
    20.
    发明公开
    PROCESS FOR FILLING ETCHED HOLES 审中-公开
    填充蚀刻孔的过程

    公开(公告)号：EP3259134A1

    公开(公告)日：2017-12-27

    申请号：EP16702736.6

    申请日：2016-02-03

    Applicant: Memjet Technology Limited

    Inventor： NORTH, Angus ,  O'REILLY, Ronan ,  MCAVOY, Gregory

    IPC: B41J2/16 ,  B81C1/00

    CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

    Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

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