公开(公告)号：WO2011094302A2

公开(公告)日：2011-08-04

申请号：PCT/US2011022565

申请日：2011-01-26

Applicant: MICROSTAQ INC ,  ARUNASALAM PARTHIBAN

Inventor： ARUNASALAM PARTHIBAN

IPC: H01L21/027

CPC classification number: H01L21/302 ,  B81C1/00611 ,  B81C2201/0121 ,  B81C2203/036 ,  H01L21/02057

Abstract: A non-abrading method to facilitate bonding of semiconductor components, such as silicon wafers, that have micro structural defects in a bonding interface surface. In a preferred method, micro structural defects are removed by forming an oxide layer on the bonding interface surface to a depth below the level of the defect, and then removing the oxide layer to expose a satisfactory surface for bonding, thereby increasing line yield and reducing scrap triggers in fabrication facilities.

Abstract translation: 一种非磨损方法，用于促进在键合界面表面中具有微结构缺陷的半导体组件（例如硅晶片）的键合。 在优选的方法中，通过在键合界面表面上形成氧化层到缺陷水平以下的深度，然后去除氧化层以暴露出令人满意的键合表面，从而增加线产量并减少 生产设施中的废料触发器。

公开(公告)号：EP2852644A1

公开(公告)日：2015-04-01

申请号：EP13794728.9

申请日：2013-05-21

Applicant: BASF SE

Inventor： NOLLER, Bastian Marten ,  GILLOT, Christophe ,  FRANZ, Diana ,  LI, Yuzhuo

IPC: C09G1/02 ,  H01L21/304 ,  H01L21/306

CPC classification number: C09G1/02 ,  B81C2201/0121 ,  B81C2201/0123 ,  B81C2201/0126 ,  H01L21/02024 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/461

Abstract: A process for the manufacture of semiconductor devices comprising the chemical-mechanical polishing of a substrate or layer containing at least one lll-V material in the presence of a chemical-mechanical polishing composition (Q1) comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) at least one amphiphilic non-ionic surfactant having (b1) at least one hydrophobic group; and (b2) at least one hydrophilic group selected from the group consisting of polyoxyalkylene groups comprising (b22) oxyalkylene monomer units other than oxyethylene monomer units; and (M) an aqueous medium.

公开(公告)号：EP1016620A2

公开(公告)日：2000-07-05

申请号：EP99204209.3

申请日：1999-12-09

Applicant: EASTMAN KODAK COMPANY

Inventor： Jech, Joseph, Jr., Patent Legal Staff ,  Lebens, John A., Patent Legal Staff ,  Brazas, John C., Jr., Patent Legal Staff

IPC: B81C1/00 ,  H01L21/3105 ,  H01L21/321

CPC classification number: B81C1/00611 ,  B81C2201/0121

Abstract: A method for producing co-planar surface areas is disclosed. At first a first layer with at least one recess is provided. Onto the first layer a second layer is deposited over the entire area of the first layer wherein the second layer has a thickness greater than the depth of the recess. The second layer is composed of material different to the material of the first layer. The next step removes the second layer completely beyond the area of at least one recess. The remaining portion of the second layer is removed until the second layer is coplanar with the first layer.

Abstract translation: 公开了一种制造共面表面区域的方法。 首先提供具有至少一个凹部的第一层。 在第一层上，第二层沉积在第一层的整个区域上，其中第二层的厚度大于凹槽的深度。 第二层由与第一层材料不同的材料组成。 下一步骤将第二层完全超过至少一个凹部的区域。 去除第二层的剩余部分直到第二层与第一层共面。

公开(公告)号：JP6336009B2

公开(公告)日：2018-06-06

申请号：JP2016220903

申请日：2016-11-11

Applicant: キヤノン株式会社

Inventor： クスナトディノフ ニャーズ ,  ラブレイク エル ドウェイン

IPC: B29C59/02 ,  H01L21/027 ,  H01L21/3065

CPC classification number: H01L21/0273 ,  B81C1/00611 ,  B81C2201/0118 ,  B81C2201/0121 ,  B81C2201/0126 ,  H01L21/28194 ,  H01L21/30604 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/7684

公开(公告)号：JP2004228085A

公开(公告)日：2004-08-12

申请号：JP2004010695

申请日：2004-01-19

Applicant: Agilent Technol Inc ,  アジレント・テクノロジーズ・インクAgilent Technologies, Inc.

Inventor： WONG MARVIN GLENN ,  CARSON PAUL THOMAS

IPC: H01H29/30 ,  B81C1/00 ,  H01H1/00 ,  H01H29/06

CPC classification number: B81C1/00611 ,  B81B2201/018 ,  B81C2201/0121 ,  H01H1/0036 ,  H01H2029/008

Abstract: PROBLEM TO BE SOLVED: To avoid increasing or decreasing by a sticky material of a cavity volume defined by a channel provided on a substrate forming a liquid metal switch .
SOLUTION: Deposition materials are deposited on a channel plate to be positioned correctly to one or a plurality of channels 102, 104, 106, or the like formed in a channel plate 100. For that purpose, (1) resist free from wetting by the deposition materials is filled in at least one (e.g. channel 104) of the plurality of channels, (2) the materials are deposited at a part (e.g. region 112) contacting at least a boundary of a part of the filled resist that is also at least one region of the channel plate 100, then (3) the resist is eliminated. As a result, an end part of the deposition materials and an end part of the channel are aligned, so that the cavity volume defined by the channel becomes stable.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：US20170349431A1

公开(公告)日：2017-12-07

申请号：US15623267

申请日：2017-06-14

Applicant: Memjet Technology Ltd.

Inventor： Angus North ,  Ronan O'Reilly ,  Gregory McAvoy

IPC: B81C1/00 ,  B41J2/16

CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a photoimageable thermoplastic polymer onto the frontside surface and into each hole; (ii) reflowing the polymer; (iii) selectively removing the polymer from regions outside a periphery of each hole, the selective removing comprising exposure and development of the polymer; (iv) optionally repeating steps (i) to (iii) until each hole is overfilled with the polymer; and (v) planarizing the frontside surface to provide one or more holes filled with a plug of the polymer. Each plug has a respective upper surface coplanar with the frontside surface.

公开(公告)号：US20160264410A1

公开(公告)日：2016-09-15

申请号：US15162997

申请日：2016-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81C1/00

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

公开(公告)号：US07352266B2

公开(公告)日：2008-04-01

申请号：US10994704

申请日：2004-11-20

Applicant: Chia-Shing Chou

Inventor： Chia-Shing Chou

IPC: H01H51/22

CPC classification number: B81C1/00611 ,  B81C2201/0121 ,  H01H59/0009 ,  H01H2059/0072 ,  Y10T29/49105

Abstract: A head electrode region for an electromechanical device is presented, comprising a first insulating layer having electrode region edges; and a head electrode, where the head electrode comprises a locking portion, with the locking portion surrounding the electrode region edges of the first insulating layer such that the head electrode is held fixed relative to the first insulating layer. The head electrode region can further comprise a top region residing above the first insulating layer and a contact region residing below the first insulator, the head electrode region further comprising a second insulating layer formed to cover at least a portion of the top region of the head electrode.

Abstract translation: 本发明提供了一种机电装置的头电极区域，包括具有电极区域边缘的第一绝缘层; 以及头电极，其中所述头电极包括锁定部分，所述锁定部分围绕所述第一绝缘层的电极区域边缘，使得所述头电极相对于所述第一绝缘层保持固定。 磁头电极区域可以进一步包括位于第一绝缘层上方的顶部区域和位于第一绝缘体下方的接触区域，所述磁头电极区域还包括形成为覆盖磁头的顶部区域的至少一部分的第二绝缘层 电极。

公开(公告)号：US07101724B2

公开(公告)日：2006-09-05

申请号：US10994703

申请日：2004-11-20

Applicant: Chia-Shing Chou

Inventor： Chia-Shing Chou

IPC: H01L21/20

CPC classification number: B81C1/00611 ,  B81C2201/0121 ,  H01H59/0009 ,  H01H2059/0072 ,  Y10T29/49105

Abstract: The present invention relates to MEM switches. More specifically, the present invention relates to a system and method for making MEM switches having a common ground plane. One method for making MEM switches includes: patterning a common ground plane layer on a substrate; forming a dielectric layer on the common ground plane layer; depositing a DC electrode region through the dielectric layer to contact the common ground plane layer; and depositing a conducting layer on the DC electrode region so that regions of the conducting layer contact the DC electrode region, so that the common ground plane layer provides a common ground for the regions of the conducting layer.

Abstract translation: 本发明涉及MEM开关。 更具体地，本发明涉及一种用于制造具有公共接地层的MEM开关的系统和方法。 制造MEM开关的一种方法包括：在衬底上构图公共接地层; 在公共接地层上形成介电层; 通过所述电介质层沉积DC电极区域以接触所述公共接地层; 以及在所述直流电极区域上沉积导电层，使得所述导电层的区域接触所述直流电极区域，使得所述公共接地层提供所述导电层的区域的公共接地。

公开(公告)号：US06911611B2

公开(公告)日：2005-06-28

申请号：US10941350

申请日：2004-09-14

Applicant: Marvin Glenn Wong ,  Paul Thomas Carson

Inventor： Marvin Glenn Wong ,  Paul Thomas Carson

IPC: H01H29/30 ,  B81C1/00 ,  H01H1/00 ,  H01H29/06 ,  H01H29/00

CPC classification number: B81C1/00611 ,  B81B2201/018 ,  B81C2201/0121 ,  H01H1/0036 ,  H01H2029/008

Abstract: A method for depositing material on a channel plate such that the material is registered to one or more channels formed in the channel plate includes filling at least one of the channels with a resist that is not wetted by the material; depositing the material on at least a region of the channel plate that includes at least part of the resist, the material registering with at least one channel edge as a result of the material's abutment to the resist; and then removing the resist. The method may be used, in one embodiment, to apply an adhesive or gasket material that is used in assembling a switch.