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11.发明公开
公开(公告)号：EP3382402A1
公开(公告)日：2018-10-03
申请号：EP18163897.4
申请日：2018-03-26
Applicant: Seiko Epson Corporation
Inventor： TANAKA, Satoru
IPC: G01P15/125 , G01P15/08
CPC classification number: B81C1/00166 , B60R16/0231 , B60R25/24 , B81B3/0008 , B81B2201/0235 , B81B2201/0242 , B81B2203/04 , B81B2207/07 , B81C2201/0133 , B81C2201/0187 , G01P15/125 , G01P2015/0831
Abstract: A manufacturing method of a physical quantity sensor includes forming a first fixed electrode, a second fixed electrode, and a dummy electrode on a substrate; and a movable body forming. The electrode forming includes forming a first mask layer on the substrate, forming a first electrode material layer by forming a first conductive layer on the substrate and the first mask layer, forming a second conductive layer on the substrate and the first electrode material layer, forming a second mask layer by forming a mask material layer on the second conductive layer, and removing a part of a section of the mask material layer not overlapping the first electrode material layer in plan view, and forming a second electrode material layer by etching the second conductive layer, with the second mask layer as a mask such that the second conductive layer is provided on the first electrode material layer and on the substrate.
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12.发明公开THREE-DIMENSIONAL CRYSTALLINE, HOMOGENOUS, AND HYBRID NANOSTRUCTURES FABRICATED BY ELECTRIC FIELD DIRECTED ASSEMBLY OF NANOELEMENTS 审中-公开BY用品领域产生了三周晶，统一和混合性纳米结构可控组装纳米元件的
公开(公告)号：EP2867018A4
公开(公告)日：2016-06-08
申请号：EP13810095
申请日：2013-07-01
Applicant: UNIV NORTHEASTERN
Inventor： BUSNAINA AHMED , YILMAZ CIHAN , KIM TAEHOON , SOMU SIVASUMBRAMANIAN
IPC: B32B9/00 , B81C1/00 , C25D5/02 , C25D13/02 , H01L21/288 , H01L21/76 , H01L21/768
CPC classification number: C25D13/18 , B23K31/00 , B81B2203/0361 , B81B2207/056 , B81C1/00111 , B81C2201/0187 , C25D3/48 , C25D5/02 , C25D13/02 , C25D13/12 , C25D13/22 , H01L21/2885 , H01L21/76879 , H01L21/76885 , H01L2221/1094
Abstract: A variety of homogeneous or layered hybrid nanostructures are fabricated by electric field-directed assembly of nanoelements. The nanoelements and the fabricated nanostructures can be conducting, semi-conducting, or insulating, or any combination thereof. Factors for enhancing the assembly process are identified, including optimization of the electric field and combined dielectrophoretic and electrophoretic forces to drive assembly. The fabrication methods are rapid and scalable. The resulting nano structures have electrical and optical properties that render them highly useful in nanoscale electronics, optics, and biosensors.
Abstract translation: 各种均相或非层状混合纳米结构的由纳米元件的电场指导组装而制造的。 纳米元件和制造的纳米结构可被导通，半导电或绝缘，或它们的任何组合。 用于提高组装过程的因素进行确定，包括电场的优化和组合介电电泳和电泳力，以驱动组件。 制作方法是快速和可扩展性。 所产生的纳米结构具有电学和光学性质做了使它们在纳米电子学，光学，和生物传感器非常有用。
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公开(公告)号：US20180016132A1
公开(公告)日：2018-01-18
申请号：US15646161
申请日：2017-07-11
Applicant: Infineon Technologies AG
Inventor： Matthias Koenig , Guenther Ruhl
CPC classification number: B81B3/0072 , B81B2201/0257 , B81B2203/0127 , B81C1/00158 , B81C1/00476 , B81C2201/0109 , B81C2201/0187 , B81C2201/0197
Abstract: A layer structure may include a carrier, a two-dimensional layer, and a holding structure. The holding structure is arranged on the carrier and holds the two-dimensional layer on the carrier such that at least a portion of the two-dimensional layer is spaced apart from the carrier. The holding structure includes a holding portion extending from the two-dimensional layer towards the carrier beyond the at least a portion of the two-dimensional layer spaced apart from the carrier.
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公开(公告)号：US20170113928A1
公开(公告)日：2017-04-27
申请号：US15400665
申请日：2017-01-06
Inventor： Andreas GOEHLICH , Andreas JUPE , Holger VOGT
CPC classification number: B81C1/00619 , B81B7/0003 , B81B2201/0207 , B81B2201/0214 , B81B2201/042 , B81C1/0019 , B81C2201/0187 , H01L23/4821 , H01L23/5256
Abstract: What is described is a method for producing a device having providing a substrate having an electrode which is exposed at a main side of the substrate. In addition, the method has forming a micro or nanostructure which has a spacer which is based on the electrode, wherein forming has the steps of: depositing a sacrificial layer on the main side, wherein the sacrificial layer has amorphous silicon or silicon dioxide; patterning a hole and/or trench into the sacrificial layer by means of a DRIE process; coating the sacrificial layer by means of ALD or MOCVD so that material of the nano or microstructure forms at the hole and/or trench, and removing the sacrificial layer.
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15.发明申请RIGID MASK FOR PROTECTING SELECTIVE PORTIONS OF A CHIP, AND USE OF THE RIGID MASK 有权用于保护芯片的选择部分的刚性掩模，以及刚性掩模的使用公开(公告)号：US20160167046A1
公开(公告)日：2016-06-16
申请号：US14831072
申请日：2015-08-20
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Alessandro Paolo BRAMANTI
IPC: B01L3/00
CPC classification number: B01L3/50853 , B01J19/0046 , B01J2219/00317 , B01J2219/00427 , B01J2219/0043 , B01J2219/00619 , B01L3/502707 , B01L3/502715 , B01L7/52 , B01L2200/02 , B01L2200/025 , B01L2200/14 , B01L2300/0609 , B01L2300/0636 , B01L2300/0645 , B01L2300/08 , B01L2300/0829 , B01L2300/12 , B01L2300/161 , B01L2300/165 , B01L2300/1805 , B29C35/0894 , B29C59/14 , B29K2995/0093 , B81C1/00206 , B81C1/00404 , B81C2201/0187
Abstract: A rigid mask protects selective portions of a chip including a plurality of wells for biochemical reactions. The rigid mask includes a supporting portion and a plurality of legs, where each leg is provided with a rigid stem and a plate. The plurality of legs are arranged and fixed with respect to the supporting portion in a way aligned to the spatial arrangement of the wells, and are configured in such a way that, when each leg is inserted into the corresponding well, the respective plate covers at least in part the bottom of the well, protecting it during a chemical/physical treatment of side walls of the wells.
Abstract translation: 刚性掩模保护包括用于生物化学反应的多个孔的芯片的选择性部分。 刚性掩模包括支撑部分和多个腿部，其中每个腿部设置有刚性杆和板。 多个支腿相对于支撑部分以与井的空间布置对准的方式布置和固定，并且被构造成使得当每个支腿插入对应的井中时，相应的板覆盖在 至少部分是井的底部，在井的侧壁的化学/物理处理期间保护它。
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Patent Agency Ranking
公开(公告)号：US20150037597A1
公开(公告)日：2015-02-05
申请号：US14259628
申请日：2014-04-23
Inventor： Chang-Koo Kim , Sung-Woon Cho
CPC classification number: C23F1/12 , B22F1/0018 , B22F1/0044 , B22F9/02 , B22F2001/0037 , B22F2304/05 , B81C1/00492 , B81C2201/0187 , B81C2201/034 , C23C18/1605 , C23C18/1657 , C23C18/1893 , C23C18/405 , C23F4/00 , H01J2237/0203 , H01J2237/3341 , H01L21/288 , Y10T29/49982
Abstract: This invention relates to a method of fabricating a three-dimensional copper nanostructure, including manufacturing a specimen configured to include a SiO2 mask; performing multi-directional slanted plasma etching to form a three-dimensional etching structure layer on the specimen; performing plating so that a multi-directional slanted plasma etched portion of the specimen is filled with a metal; removing an over-plated portion and the SiO2 mask from the metal layer; and removing a portion of a surface of the specimen other than the metal which is the three-dimensional etching structure layer. In this invention, a uniform copper nanostructure array can be obtained by subjecting a large-area specimen disposed in a Faraday cage to multi-directional slanted plasma etching using high-density plasma, forming a copper film on the etched portion of the specimen, and removing an over-plated copper film and the SiO2 mask, and the diameter of the copper nanostructure can be arbitrarily adjusted, thus attaining high applicability.
Abstract translation: 本发明涉及一种制造三维铜纳米结构的方法，包括制造被配置为包括SiO 2掩模的试样; 执行多方向倾斜等离子体蚀刻以在样本上形成三维蚀刻结构层; 进行电镀，使得样品的多方向倾斜等离子体蚀刻部分被金属填充; 从金属层去除过镀层部分和SiO 2掩模; 除去除了作为三维蚀刻结构层的金属以外的试样的表面的一部分。 在本发明中，通过对设在法拉第笼中的大面积试样进行多层倾斜等离子体蚀刻，使用高密度等离子体，在试样的蚀刻部分上形成铜膜，可以得到均匀的铜纳米结构体， 去除过镀铜膜和SiO 2掩模，并且可以任意调整铜纳米结构的直径，从而获得高适用性。
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公开(公告)号：US20040048484A1
公开(公告)日：2004-03-11
申请号：US10235166
申请日：2002-09-05
Inventor： Maurice S. Karpman , Swaminathan Rajaraman
IPC: H01L021/302 , H01L021/461
CPC classification number: B81C1/00373 , B81C2201/0187 , H04Q2213/1301
Abstract: A method of producing a shadow mask having a set of apertures (the set of apertures including a given aperture with an aperture boundary) uses a wafer having at least a first silicon layer, a second silicon layer, and an insulator layer between the first and second silicon layers. A first portion of the first silicon layer within the aperture boundary is removed. This produces a second portion of the first silicon layer, which remains within the aperture boundary. The second silicon layer within the aperture boundary is removed, as well as the insulator layer within the aperture boundary. The second portion of the first silicon layer remaining within the aperture boundary then is removed.
Abstract translation: 一种制造具有一组孔径（包括具有孔径边界的给定孔径的一组孔口）的荫罩的方法使用具有至少第一硅层，第二硅层和绝缘体层的晶片，所述第一硅层和第二硅层在第一和第 第二硅层。 去除孔边界内的第一硅层的第一部分。 这产生了保留在孔边界内的第一硅层的第二部分。 孔边界内的第二硅层以及孔边界内的绝缘体层被去除。 剩余在孔边界内的第一硅层的第二部分被去除。
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公开(公告)号：US20190219919A1
公开(公告)日：2019-07-18
申请号：US16330839
申请日：2017-09-12
Applicant: 3M INNOVATIVE PROPERTIES COMPANY
Inventor： James Zhu , Daniel M. Lentz , Karl K. Stensvad , David J. Tarnowski
CPC classification number: G03F7/0002 , B81C1/00031 , B81C2201/0187 , B82Y40/00 , C25F3/14 , C25F7/00
Abstract: A method of patterning a cylindrical tool, including providing a stamp including a base and a layer of solid state ionic conductor thereon, applying a negative of a predetermined pattern of features on a major surface of the solid state ionic conductor, providing a cylindrical tool having a metallic surface positioned proximate the stamp, and applying an electric field between the metallic surface and a cathode while moving the stamp against the metallic surface in rolling line contact so as to impart the predetermined pattern of features onto the metallic surface, wherein the cathode is either the base or a conductive element positioned adjacent to the base. The positive of the predetermined pattern of features may include a multiplicity of nano-sized features.
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19.发明申请公开(公告)号：US20180273375A1
公开(公告)日：2018-09-27
申请号：US15900088
申请日：2018-02-20
Applicant: Seiko Epson Corporation
Inventor： Satoru TANAKA
IPC: B81C1/00 , B81B3/00 , B60R25/24 , B60R16/023
CPC classification number: B81C1/00166 , B60R16/0231 , B60R25/24 , B81B3/0008 , B81B2201/0235 , B81B2201/0242 , B81B2203/04 , B81B2207/07 , B81C2201/0133 , B81C2201/0187 , G01P15/125 , G01P2015/0831
Abstract: A manufacturing method of a physical quantity sensor includes forming first and second fixed electrodes, and a dummy electrode on a substrate; and a movable body forming. The electrode forming includes forming a first mask layer on the substrate, forming a first electrode material layer by forming a first conductive layer on the substrate and the first mask layer, forming a second conductive layer on the substrate and the first electrode material layer, forming a second mask layer by forming a mask material layer on the second conductive layer, and removing a part of a section of the mask material layer not overlapping the first electrode material layer in plan view, and forming a second electrode material layer by etching the second conductive layer, with the second mask layer as a mask such that the second conductive layer is provided on the first electrode material layer and on the substrate.
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公开(公告)号：US20170332179A1
公开(公告)日：2017-11-16
申请号：US15596458
申请日：2017-05-16
Inventor： VICTOR M. BRIGHT , JOSEPH J. BROWN
CPC classification number: H04R23/002 , B81C1/00158 , B81C2201/0187 , B82B3/0009 , B82B3/0038 , B82B3/0042 , B82Y40/00 , H01L51/0097 , H04R31/00
Abstract: In one aspect, the present invention provides nano-scale heaters, such as nano-scale thermoacoustic loudspeakers comprising suspended metal nanobridges prepared using atomic layer deposition (ALD). The loudspeakers of the invention are capable of producing audible sound when stimulated with an electrical current or other energetic stimulus. In another aspect, the present invention provides methods of preparing and using such nanodevices.
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