公开(公告)号：KR1020090053872A

公开(公告)日：2009-05-28

申请号：KR1020070120561

申请日：2007-11-24

Applicant: 인하대학교 산학협력단

Inventor： 윤광섭 ,  주찬양

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M2201/61 ,  H03M2201/6372 ,  H03M2201/644 ,  H03M2201/932

Abstract: 본 발명은 디지털-아날로그 변환기에 관한 것으로서, 이진 디코더 구조를 갖는 디지털-아날로그 변환기에 관한 것이다.
본 발명은 N비트(bit)의 디지털 데이터를 입력받아 N개의 입력신호를 출력하는 입력 버퍼부(100)와, N개의 입력 신호를 입력받아 2
N -1개의 출력 신호를 출력하는 이진 디코더부와, 2
N -1개의 출력 신호를 입력받아 2(2
N -1)개의 차동 출력 신호를 출력하는 스위치 구동부와, 바이어스(bias)로부터 기준 전류와 바이어스 전압을 인가받고 스위치 구동부의 출력 신호를 입력받아 비반전 출력전류와 반전 출력전류를 출력하는 전류원 셀부, 및 비반전 출력전류와 반전 출력전류를 인가받아 출력전압으로 변환시키는 부하 저항부를 포함한다.
상기와 같은 본 발명은 전류원 부정합에 의한 글리치를 줄이고, 출력 신호의 선형성을 향상시켜 디지털-아날로그 변환기의 정적 성능과 동적 성능을 향상시키는 효과가 있다.
디지털-아날로그 변환기, DAC, 이진 디코더

公开(公告)号：KR1020080083470A

公开(公告)日：2008-09-18

申请号：KR1020070024079

申请日：2007-03-12

Applicant: 삼성전자주식회사

Inventor： 최진우 ,  이승훈 ,  송민규 ,  황상훈 ,  이동진 ,  신승철

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/002 ,  H03M1/06 ,  H03M2201/62 ,  H03M2201/644 ,  H03M2201/814

Abstract: A switching decoder and a current steering digital/analog converter including the same are provided to reduce a glitch by adjusting a size of a PMOS(P-Channel Metal-Oxide Semiconductor) transistor. A switching decoder includes a digital logic circuit(100), and a latch-deglitch circuit(200). The digital logic circuit receives digital signals and generates a couple of control signals. The latch-deglitch circuit has a couple of first transistors and a couple of second transistors. The first transistors receive the couple of control signals, synchronize and output the received control signals with a clock signal. The second transistors are cascade-coupled with the first transistors. The second transistors have a couple of PMOS transistors. Drains of the first transistors cross gates of the second transistors.

Abstract translation: 提供了一种开关解码器和包括该开关解码器的电流转向数字/模拟转换器，以通过调整PMOS（P沟道金属氧化物半导体）晶体管的尺寸来减少毛刺。 开关解码器包括数字逻辑电路（100）和锁存 - 反跳路电路（200）。 数字逻辑电路接收数字信号并产生一对控制信号。 锁存 - 跳跃电路具有一对第一晶体管和一对第二晶体管。 第一晶体管接收一对控制信号，使用时钟信号同步并输出接收到的控制信号。 第二晶体管与第一晶体管级联耦合。 第二晶体管具有一对PMOS晶体管。 第一晶体管的漏极交叉第二晶体管。

公开(公告)号：KR1020040099883A

公开(公告)日：2004-12-02

申请号：KR1020030032013

申请日：2003-05-20

Applicant: 학교법인 정석인하학원

Inventor： 윤광섭 ,  조현호

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/0863 ,  H03M2201/644 ,  H03M2201/814 ,  H03M2201/931

Abstract: PURPOSE: A deglitch circuit for improving performance of a digital/analog converter to execute a high-speed data transmission/reception operation is provided to improve the frequency capacity by minimizing the glitch energy. CONSTITUTION: A first PMOS transistor(M1) includes a gate for receiving a positive input signal and is turned on or off according to a logical state of the positive input signal. A first NMOS transistor(M3) includes a drain connected to a drain of the first PMOS transistor, a gate for receiving the positive input signal, and is turned on or off according to the logical state of the positive input signal. A third NMOS transistor(M5) includes a drain connected to a source of the first PMOS transistor, a gate for receiving the positive input signal, and is turned on or off according to the logical state of the positive input signal. A second PMOS transistor(M2) includes a gate for receiving a negative input signal and is turned on or off according to a logical state of the negative input signal. A second NMOS transistor(M4) includes a drain connected to a drain of the second PMOS transistor, a gate for receiving the negative input signal, and is turned on or off according to the local state of the negative input signal. A fourth NMOS transistor(M6) includes a drain connected to a source of the second PMOS transistor, a gate for receiving the negative input signal, and is turned on or off according to the local state of the negative input signal.

Abstract translation: 目的：提供一种用于提高数字/模拟转换器执行高速数据发送/接收操作性能的去电泳电路，通过最小化故障能量来提高频率容量。 构成：第一PMOS晶体管（M1）包括用于接收正输入信号的栅极，并根据正输入信号的逻辑状态导通或截止。 第一NMOS晶体管（M3）包括连接到第一PMOS晶体管的漏极的漏极，用于接收正输入信号的栅极，并且根据正输入信号的逻辑状态导通或截止。 第三NMOS晶体管（M5）包括连接到第一PMOS晶体管的源极的漏极，用于接收正输入信号的栅极，并且根据正输入信号的逻辑状态导通或截止。 第二PMOS晶体管（M2）包括用于接收负输入信号的栅极，并根据负输入信号的逻辑状态导通或截止。 第二NMOS晶体管（M4）包括连接到第二PMOS晶体管的漏极的漏极，用于接收负输入信号的栅极，并且根据负输入信号的本地状态导通或截止。 第四NMOS晶体管（M6）包括连接到第二PMOS晶体管的源极的漏极，用于接收负输入信号的栅极，并且根据负输入信号的本地状态导通或截止。

公开(公告)号：KR1020000018464A

公开(公告)日：2000-04-06

申请号：KR1019980036054

申请日：1998-09-02

Applicant: 현대반도체 주식회사

Inventor： 장성진

IPC: H03M1/66

CPC classification number: H03M1/0863 ,  H03M1/66 ,  H03M2201/644

Abstract: PURPOSE: A digital/analog converter is provided to restrict a noise generated from an output power of a current cell by using a signal level controller for driving a power source. CONSTITUTION: The digital/analog converter comprises: an OR/AND buffer(21) for outputting a power voltage as a general logical value and a power source driving signal having a level of grounding after performing a logical operation for a digital signal formed by decoding each current cell of current cell matrix; a power source(23) for outputting a constant current according to the power source driving signal; a signal level controller(22) for driving the current source by controlling the level of the current source driving signal from the OR/AND buffer.

Abstract translation: 目的：提供数字/模拟转换器，通过使用用于驱动电源的信号电平控制器来限制从当前单元的输出功率产生的噪声。 构成：数字/模拟转换器包括：用于输出作为一般逻辑值的电源电压的或/和缓冲器（21），以及在对通过解码形成的数字信号执行逻辑运算后具有接地电平的电源驱动信号 当前单元矩阵的每个当前单元; 电源（23），用于根据电源驱动信号输出恒定电流; 信号电平控制器（22），用于通过控制来自OR / AND缓冲器的电流源驱动信号的电平来驱动电流源。